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madhub86
Observer
Observer
3,499 Views
Registered: ‎09-01-2014

Can I use the IP core of an ISE in EDK?

Hi,

 

I want to use the IP core of PCI express which is available in ISE in EDK, which means I should import all the verilog modules of ISE IP core to EDK. Is this possible, if possible please send related documents.

 

Thanks & Regards,

Madhu.B

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8 Replies
vsrunga
Xilinx Employee
Xilinx Employee
3,496 Views
Registered: ‎07-11-2011

Hi,

 

Please check below links

 

https://sites.google.com/a/cs.ship.edu/fpga/xilinx-tricks/include-coregenerator-ip-in-edk

 

https://www.youtube.com/watch?v=j6GX9z-C2Us

 

http://forums.xilinx.com/t5/Embedded-Development-Tools/Coregen-files-in-custom-Pcore-User-Logic-Trouble-getting/td-p/67203

 

http://forums.xilinx.com/t5/Embedded-Development-Tools/Put-Coregen-component-into-EDK-library/td-p/20886

 

Hope this helps

 

-Vanitha

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siktap
Scholar
Scholar
3,474 Views
Registered: ‎06-14-2012

Yes you can. 

http://www.xilinx.com/support/answers/22882.htm

Please check this. Hope this helps.

 

Regards

Sikta

 

 

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balkris
Xilinx Employee
Xilinx Employee
3,460 Views
Registered: ‎08-01-2008

Please find the attached document.

Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
3,459 Views
Registered: ‎08-01-2008

Below link may help you

https://sites.google.com/a/cs.ship.edu/fpga/xilinx-tricks/include-coregenerator-ip-in-edk
Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
3,454 Views
Registered: ‎08-01-2008

you can check below ARs
http://www.xilinx.com/support/answers/37856.html
Thanks and Regards
Balkrishan
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madhub86
Observer
Observer
3,432 Views
Registered: ‎09-01-2014

Hi

 

I want to use IP core of ISE in EDK, the answer record you have provided is reverse. Can you please send if there is any AR related to my query. If possible please provide documents. My operating System is windows.

 

Thanks,

Madhu

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madhub86
Observer
Observer
3,427 Views
Registered: ‎09-01-2014

Hi,

 

Thanks for the reply and for the link you have provided.

 

My query is in the last step you are able to view all the signals but in my project i am getting only below signals in .mhs file

 

BEGIN clk_50
PARAMETER INSTANCE = clk_50_0
PARAMETER HW_VER = 1.00.a
END

 

When i am trying to edit the .mhs file it is showing the following error

 

ERROR:EDK:4085 - IPNAME: clk_50, INSTANCE: clk_50_0 - PARAMETER CLKIN1_IN not found in the MPD - F:\pallani\ISE_EDK\system.mhs line 123

 

Can you please help me out to solve the issue

 

Thanks 

Madhu

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madhub86
Observer
Observer
3,316 Views
Registered: ‎09-01-2014

Hi

 

I have followed all the steps shown in the below link

 

http://forums.xilinx.com/xlnx/attachments/xlnx/NewUser/15250/1/coregen_clock_in_edk.pdf

 

My query is in the last step you are able to view all the signals but in my project i am getting only below signals in .mhs file

 

BEGIN clk_50
PARAMETER INSTANCE = clk_50_0
PARAMETER HW_VER = 1.00.a
END

 

When i am trying to edit the .mhs file it is showing the following error

 

ERROR:EDK:4085 - IPNAME: clk_50, INSTANCE: clk_50_0 - PARAMETER CLKIN1_IN not found in the MPD - F:\pallani\ISE_EDK\system.mhs line 123

 

Can you please help me out to solve this issue. please its urgent

 

Thanks

Madhu

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