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Visitor samberhanu
Visitor
5,371 Views
Registered: ‎07-29-2014

Cannot set LOC property of ports error even with 2014.1 in using the OSERDES primitve

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I tried to syntehsize a design. Currently, the only constraint i've included are LOC constraints on pins that I want to use for an FMC 110 card that connects both to the LPC & HPC sites on the Kintex board. The design synthesizes fine but during Implementation it gives me the following error:

[Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance dac_interface/serdes_data_interfaceI/oserdes_buffers[0].obufds_inst at P21 (IOB_X0Y212) since it belongs to a shape containing instance dac_interface/serdes_data_interfaceI/oserdes_buffers[0].iodelay_inst. The shape requires relative placement between dac_interface/serdes_data_interfaceI/oserdes_buffers[0].obufds_inst and dac_interface/serdes_data_interfaceI/oserdes_buffers[0].iodelay_inst that cannnot be honored because it would result in an invalid location for dac_interface/serdes_data_interfaceI/oserdes_buffers[0].iodelay_inst. 

part of the mystery about this to me is, when the same design is implemented in ISE, it goes through with implementation and bit file generation without a hickup. When looking at the implemented design, the LOC pins have been changed to other sites than what I had had originally intended to use for I/O interfacing. (this is critical since I can't do data conversion with just any pin) The serdes OLOGIC all are there wired to different IOB sites. It's as if the fabric routing gets optimized ahead of the SERDES, & then the tool moves stuff around for pin LOCs b/c it wants to reduce the path length (I don't have ANY clock constraints at the moment for right now).

I don't have any cell LOC constraints, but I am a bit confused also on what to LOC for/as a cell constraint. Is it the bufds, &/or the OLOGIC? I hope this was not confusing. I am relatively new, willing to read, just sometimes it is overwhelming to clearly understand everything.

 

here is an example of one of the pins constraints i have in the xdc file (i've 16 diff pairs for the I & Q DAC signals)

set_property PACKAGE_PIN P21 [get_ports {dacI_data_serdes_n[0]}]
# FMC_HPC_LA32_P
set_property IOSTANDARD LVDS_25 [get_ports {dacI_data_serdes_n[0]}]
# FMC_HPC_LA32_P
set_property PACKAGE_PIN R21 [get_ports {dacI_data_serdes_p[0]}]
# FMC_HPC_LA32_N
set_property IOSTANDARD LVDS_25 [get_ports {dacI_data_serdes_p[0]}]
# FMC_HPC_LA32_N

but after the critical warning, P21 gets moved to A12 without any idelay2 connection i can see from the device view in vivado after implementation. Ofcourse, after the critical warning, the bit file generation fails.

 

 

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Visitor samberhanu
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4,714 Views
Registered: ‎07-29-2014

Re: Cannot set LOC property of ports error even with 2014.1 in using the OSERDES primitve

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just in case someone is interested, the issue was that in the 7-series HR banks don't support ODELAYs, only HP banks. Vivado, being the stricter between it and ISE, wouldn't permit b/c you cant implement an ODELAY, while ISE on the other hand was completely removing the ODELAY and synthesizing the design without it.

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Re: Cannot set LOC property of ports error even with 2014.1 in using the OSERDES primitve

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Hi,

 

Can you share the post synthesis checkpoint (.dcp file located in project.runs-->synth_1 location)?

 

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor samberhanu
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Registered: ‎07-29-2014

Re: Cannot set LOC property of ports error even with 2014.1 in using the OSERDES primitve

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I've attached the dcp file. I just want to reiterate that the synthesis part actually works fine for both vivado & ISE. ISE implements the design without having the critical warnings i see in vivado.

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Scholar kotir
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5,309 Views
Registered: ‎02-03-2010

Re: Cannot set LOC property of ports error even with 2014.1 in using the OSERDES primitve

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Hi ,

 

Check if you have multiple XDC files with conflicting location constraints.

I have seen a scenario where user has a location constraints at IP level with one set of location constraints but in over all design he is assigning to another locations.

In such case this error pops up.

 

Regards,

KR

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Xilinx Employee
Xilinx Employee
5,304 Views
Registered: ‎09-20-2012

Re: Cannot set LOC property of ports error even with 2014.1 in using the OSERDES primitve

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Hi @samberhanu 

 

I see the below connectivity in the synthesized design.

 

It looks like ODELAYE2 output is not being used in the design. If this is true can you remove this ODELAY2 instance and see if that helps?

 

Capture.JPG

Thanks,

Deepika.

Thanks,
Deepika.
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Visitor samberhanu
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Registered: ‎07-29-2014

Re: Cannot set LOC property of ports error even with 2014.1 in using the OSERDES primitve

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Removing the Odelay instantiations seemed to work in terms of synthesis and implementation without the critical warnings. I am skeptical at what happens when I test the design at the output of the DAC sometime this afternoon.

Two questions i have though,

1) is the ODELAY necessary? (i thought it is) for OSerdes functionality.

2) why is ISE (14.7) not having a problem with synthesis and implementation, (same no connection between the iodelay) while Vivado gives me a critical warning for LOC issues? it still fails at the end in bit file generation b/c it sees there is a conflict b/n the LOC constraint and the pins that the nets have been routed to during implementation 

2a) In relation to this, why does vivado implementation move the pins during implementation to other pin sites even though the original LOC constraints were at a set of different pins?

Kotir: i don't have multiple xdcs.

Thanks for your quick response.

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Visitor samberhanu
Visitor
4,715 Views
Registered: ‎07-29-2014

Re: Cannot set LOC property of ports error even with 2014.1 in using the OSERDES primitve

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just in case someone is interested, the issue was that in the 7-series HR banks don't support ODELAYs, only HP banks. Vivado, being the stricter between it and ISE, wouldn't permit b/c you cant implement an ODELAY, while ISE on the other hand was completely removing the ODELAY and synthesizing the design without it.

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