06-15-2017 01:35 PM
Ultrascale+ MPSoC design. 64-bit PL-based DDR4 design. 2017.1 using IP Integrator.
I am trying to set the DDR interface to Ping-Pong PHY mode instead of "Controller and Physical Layer".
No matter what I do I cannot get Ping-Pong PHY mode to appear as an option in the Controller/PHY mode drop-down box (which is what PG150 seems to tell me to do). Am I missing something?
Thanks for any help.
06-16-2017 06:39 AM
It looks like you are using the MIG IP inside block design. Try generating the IP from IP catalog outside block design.
06-16-2017 09:16 AM - edited 06-16-2017 09:25 AM
Yes, you are right. Thankyou.
Seems that I can only select Ping-Pong PHY when instantiating DDR4 MIG in the non IP Integrator flow.
It is also the case that Ping-Pong PHY mode is not available when using the AXI4 interface.
Thinking about it, I guess these two "features" are related. I suppose the core would need 2 AXI interfaces in order to support Ping-Pong PHY with AXI4? This is still conceptually possible, but is clearly more complex. I assume it's just that Xilinx has just not got around to doing this yet? Do we know if Xilinx have any plan to address it? Just curious.
06-20-2017 10:05 AM
Still concerned. I have an Ultrascale+ IP Integrator .bd design which has a valid PL-DDR4 pinout defined, according to the NON-Ping-Pong PHY mode DDR interface. I used the byte-planner to set this pinout.
As far as I know (through reading and forums etc), there are only 3 pins which need to be duplicated for Ping-Pong PHY support: CSn, CKe and ODT.
Is it safe for me to simply add these additional pins to my existing non-Ping-Pong PHY design? In which case, are there recommended pin locations for the duplicated pins?
Or are there additional pins I am unaware of?
And does the non-Ping-Pong PHY pinout need to change in other ways (eg definition of byte lanes etc) or is it still valid?
I could build a design using the non-IPI core in Ping-Pong PHY mode simply in order to extract a valid placement for the additional pins. but I fear this is error-prone.