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Adventurer
Adventurer
2,746 Views
Registered: ‎03-21-2013

Cannot set MIG into Ping-Pong PHY mode

Hi

Ultrascale+ MPSoC design. 64-bit PL-based DDR4 design. 2017.1 using IP Integrator.

I am trying to set the DDR interface to Ping-Pong PHY mode instead of "Controller and Physical Layer". 

No matter what I do I cannot get Ping-Pong PHY mode to appear as an option in the Controller/PHY mode drop-down box (which is what PG150 seems to tell me to do). Am I missing something? 

Thanks for any help. 

MIG.jpg

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4 Replies
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Xilinx Employee
Xilinx Employee
2,710 Views
Registered: ‎09-20-2012

Re: Cannot set MIG into Ping-Pong PHY mode

Hi @clivewmwalker

 

It looks like you are using the MIG IP inside block design. Try generating the IP from IP catalog outside block design.

Thanks,
Deepika.
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Adventurer
Adventurer
2,700 Views
Registered: ‎03-21-2013

Re: Cannot set MIG into Ping-Pong PHY mode

Hi Deepika.

 

Yes, you are right. Thankyou.

 

Seems that I can only select Ping-Pong PHY when instantiating DDR4 MIG in the non IP Integrator flow.

It is also the case that Ping-Pong PHY mode is not available when using the AXI4 interface.

 

Thinking about it, I guess these two "features" are related. I suppose the core would need 2 AXI interfaces in order to support Ping-Pong PHY with AXI4? This is still conceptually possible, but is clearly more complex. I assume it's just that Xilinx has just not got around to doing this yet? Do we know if Xilinx have any plan to address it? Just curious.

 

Cheers

 

Clive

 

 

 

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Adventurer
Adventurer
2,614 Views
Registered: ‎03-21-2013

Re: Cannot set MIG into Ping-Pong PHY mode

Hi Deepika.

 

Still concerned. I have an Ultrascale+ IP Integrator .bd design which has a valid PL-DDR4 pinout defined, according to the NON-Ping-Pong PHY mode DDR interface. I used the byte-planner to set this pinout.

As far as I know (through reading and forums etc), there are only 3 pins which need to be duplicated for Ping-Pong PHY support: CSn, CKe and ODT. 

Is it safe for me to simply add these additional pins to my existing non-Ping-Pong PHY design? In which case, are there recommended pin locations for the duplicated pins?

Or are there additional pins I am unaware of?

And does the non-Ping-Pong PHY pinout need to change in other ways (eg definition of byte lanes etc) or is it still valid?

 

I could build a design using the non-IPI core in Ping-Pong PHY mode simply in order to extract a valid placement for the additional pins. but I fear this is error-prone. 

 

 

Clive

 

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Observer
Observer
805 Views
Registered: ‎09-19-2018

Re: Cannot set MIG into Ping-Pong PHY mode

Clearly, there are NO answers to the designer level questions.

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