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Visitor
Posts: 11
Registered: ‎05-22-2017
Accepted Solution

Clock connection in Kintex 7

Hi,

 

I am using knitex 7 FPGA in my board. 

I have interfaced differential clock to one of the HR bank, is there any restriction to access the same clock from HP bank.

 

Thanks and Regards,

Nibin Das S


Accepted Solutions
Highlighted
Teacher
Posts: 9,030
Registered: ‎08-14-2007

Re: Clock connection in Kintex 7

My recollection is that you can only supply the reference clock for IDELAYCTRL from another column.  The clock for the MIG itself, the one that generates the DDR3 interface timing, would need to be placed within the same column as the DDR3 itself.  This usually means one of the same HP banks you're using for address/ctrl/data of the DDR3 interface.  If you need to use a single 200 MHz input for both MIG timing and IDELAYCTRL reference it would need to be in the HP banks used for MIG.

-- Gabor

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Xilinx Employee
Posts: 12
Registered: ‎09-18-2014

Re: Clock connection in Kintex 7

Nibin,

 

You really need to provide more context detail here. This is an open-ended question just by looking only at your post. Which Kintex part/package are we talking about? How far are the HR and HP banks? What kind of clock is this? Global? Local? What kind of design load or loads are you targeting? What load spread are you looking at? How many of these loads will the clock be supplying? Is it all contained locally in the clocking region associated with HP bank you are talking about? HR or HP are only IO structure based distinctions. Once inside the device, it's about clocking regions. Granted a different IO bank will mean an IO buffer in a different clocking region in most cases. If you don't mind longer clock routing delay, skew issues(if loads are not local), compromising on clock quality, possible reduced timing margin caused by longer clock routes there should be no issues per say. Make sure you use appropriate clocking resources(BUFG/BUFR/MMCM/PLL) most applicable to your design and routing needs. We provide plenty of guidance on clocking if you've checked our documentation site. 

 

Quick Tips: Visit our IO and clock planning Vivado design hub page. This should have all the good docs associated with IO and clock planning for your design. 

 

https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0007-vivado-pin-planning-hub.html

 

View our IO and clock planning user guide:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug899-vivado-io-clock-planning.pdf

 

-T

Visitor
Posts: 11
Registered: ‎05-22-2017

Re: Clock connection in Kintex 7

Hi,

 

I am using Kintex 7 FPGA (XC7K160T-2FBG676I).

I have interfaced DDR3 (16 bit, 2 devices) to HP bank (33,34). I have planned to give differential clock of 200MHz (LVDS) to MRCC pins of HR (15) bank (along with 125MHz for 2 Ethernet) in order to meet the clock requirement by DDR3. Is it possible to do so.

 

Thanks and Regards,

Nibin Das S

Highlighted
Teacher
Posts: 9,030
Registered: ‎08-14-2007

Re: Clock connection in Kintex 7

My recollection is that you can only supply the reference clock for IDELAYCTRL from another column.  The clock for the MIG itself, the one that generates the DDR3 interface timing, would need to be placed within the same column as the DDR3 itself.  This usually means one of the same HP banks you're using for address/ctrl/data of the DDR3 interface.  If you need to use a single 200 MHz input for both MIG timing and IDELAYCTRL reference it would need to be in the HP banks used for MIG.

-- Gabor
Visitor
Posts: 11
Registered: ‎05-22-2017

Re: Clock connection in Kintex 7

Hi,

 

Thank you for the support.

 

Thanks and Regards,

Nibin Das S