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Visitor jgtimms
Visitor
4,544 Views
Registered: ‎07-18-2013

Clocking DDR data into a FIFO in Spartan 6

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I would appreciate if someone could show\tell me how to implement something in ISE\Verilog. 

 

I want to bring the output of an ADC into a Spartan 6 and store it in a FIFO within the FPGA.  The problem I am having is the ADC output data is LVDS and DDR, i.e. new differential data is present and should be clocked into the FIFO on both edges of a 200MHz differential clock provided by the ADC.  How to I update the FIFO on both edges of this external differential clock?

 

I appreciate your assistance.

 

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Scholar austin
Scholar
5,749 Views
Registered: ‎02-27-2008

Re: Clocking DDR data into a FIFO in Spartan 6

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j,

 

This will be very difficult, as S6 is not very fast (it is designed for lowest power, lowest cost).  Even in Virtex, this may not be the best way to solve the problem.


Rather, I would store using edge data in one BRAM/FIFO, and falling edge data in another BRAM/FIFO.


Reading back out, I would use the dual port of the FIFO to read both even and odd on a new clock, which is rising edge for both, but half the speed.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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5 Replies
Scholar austin
Scholar
5,750 Views
Registered: ‎02-27-2008

Re: Clocking DDR data into a FIFO in Spartan 6

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j,

 

This will be very difficult, as S6 is not very fast (it is designed for lowest power, lowest cost).  Even in Virtex, this may not be the best way to solve the problem.


Rather, I would store using edge data in one BRAM/FIFO, and falling edge data in another BRAM/FIFO.


Reading back out, I would use the dual port of the FIFO to read both even and odd on a new clock, which is rising edge for both, but half the speed.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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Instructor
Instructor
4,536 Views
Registered: ‎08-14-2007

Re: Clocking DDR data into a FIFO in Spartan 6

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Why not just use the IDDR2 input registers to feed one FIFO that's twice as wide?

-- Gabor
Teacher eteam00
Teacher
4,519 Views
Registered: ‎07-21-2009

Re: Clocking DDR data into a FIFO in Spartan 6

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Spartan-6 is easily capable of handling 400MS/sec DDR data with a 200MHz clock.  There are many MANY examples of source-synchronous design problems similar to what you describe, in these forums, in the Spartan-6 device family docs (see the Clocking Resources User Guide), and in the Spartan-6 reference designs for the various evaluation boards.

 

-- Bob Elkind

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Historian
Historian
4,507 Views
Registered: ‎02-25-2008

Re: Clocking DDR data into a FIFO in Spartan 6

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@eteam00 wrote:

Spartan-6 is easily capable of handling 400MS/sec DDR data with a 200MHz clock.  There are many MANY examples of source-synchronous design problems similar to what you describe, in these forums, in the Spartan-6 device family docs (see the Clocking Resources User Guide), and in the Spartan-6 reference designs for the various evaluation boards.

 

-- Bob Elkind


The question is not whether the I/O can handle that speed; it's whether he can write to a BRAM or FIFO at that speed.

----------------------------Yes, I do this for a living.
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Visitor jgtimms
Visitor
4,486 Views
Registered: ‎07-18-2013

Re: Clocking DDR data into a FIFO in Spartan 6

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This makes sense.  Thank you all.

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