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wiangtong
Newbie
Newbie
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Registered: ‎08-25-2016

Config pin as single-ended io in Zynq7000 (Trenz)

Let me confirm that we have corrected map the FPGA pin in Trenz dev board.
 
We expect to map (PL->FPGApin->FMCpin
UARTLITE.Tx -> Y18 ->  FMC_LA0_P
UARTLITE.Rx -> Y19 ->  FMC_LA0_N
 
 
This case does not  work! as single ended ports. it seems that the voltage level at P is similar to N on the same pair.
 
However, from the experiments:
TX -> LA0_P, RX -> LA0_N (Not OK)
TX -> LA0_P, RX -> LA1_P (OK)
TX -> LA0_N, RX -> LA1_N (Not OK)
 
...
...
 
Any special attribute parameters to be defined in XDC?
We need a lot of 3.3V pins as UART outputs. Is it possible to use all pins (both P and N) as a single ended pin?
 
I appreciate if you have any suggestions.
 
Best regards,
Yod
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balkris
Xilinx Employee
Xilinx Employee
4,634 Views
Registered: ‎08-01-2008

yes its possible you need to convert differential clock to single ended

you can use IBUFGDS for the clock to convert from differential clock to single.

 

For vivado you can find information here

 

http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

 

 

ISe design flow

 

See more description in the following user guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf (page no. 177)

 

check this post as well

https://forums.xilinx.com/t5/Implementation/How-do-I-tell-Vivado-that-my-signal-is-differential/td-p/332731

 

https://forums.xilinx.com/t5/General-Technical-Discussion/The-difference-between-IBUF-IBUFDS-and-IBUFG-IBUFGDS/td-p/310949

 

 

Thanks and Regards
Balkrishan
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wiangtong
Newbie
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4,619 Views
Registered: ‎08-25-2016

Thanks for you info.

There is no clock signal. We are using UARTLITE ipcore and try to use Tx, Rx as single ended ports.

It doesnot work when we map Tx, Rx on the same P/N pair. Why? 

 

BTW, we are using Trenz TE0715 with Z7030 on board.

 

Regards,

Theerayod

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balkris
Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

https://forums.xilinx.com/t5/Silicon-Devices-Others-Archived/Boundary-Scan-loading-to-SPI-Flash-failed/td-p/86347
Thanks and Regards
Balkrishan
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muzaffer
Teacher
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Registered: ‎03-31-2012

are you sure the bank which is connected to the fmc connector can do 3.3V IO ? 

what you want should certainly work. Just make sure nothing else is connected to the same pins.

 

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