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[syed_radiation]

Hello,

I trying to interface 80MHz ADC with Artix-7 FPGA (XC7A200T). 

I used "IDELAYCTRL" in my design for IDELAY2. Pls. see the snapshot of the "Implementation", "warning message", and source code. 

In implementation, it looks "IDELAYCTRL" routed properly, but why it shows, warning! 

I am having timing problem on capturing ADC output!

I am glad for your valuable reply. 

[muzaffer · Accepted solution]

@syed_radiation I don't think you need to place IDELAYCTRL cells. In any case if the yellow highlighted line is where you set the LOC property, label doesn't really seem like a valid site for a xilinx fpga. You can see what the site is by looking at the properties of the placed cell.

[muzaffer · Accepted solution]

@syed_radiation I don't think you need to place IDELAYCTRL cells. In any case if the yellow highlighted line is where you set the LOC property, label doesn't really seem like a valid site for a xilinx fpga. You can see what the site is by looking at the properties of the placed cell.

[syed_radiation]

Hello,

I defined variable as below: 

generic (
C_OnChipLvdsTerm : integer := 1;
C_AdcUseIdlyCtrl : integer := 1;
C_AdcIdlyCtrlLoc : string ;
C_BufioLoc : string ;
C_BufrLoc : string ;

C_AdcChnls : integer := 16; -- Number of ADC in a package
C_AdcBits : integer := 14
);

I didn't assign specific location in fabric. Anyway, when I comment it out below line 

-- attribute LOC of AdcToplevel_I_IdlyCtrl_0 : label is C_AdcIdlyCtrlLoc;

Still I have same warning message. 

Thanks for your kind reply.