11-28-2013 08:17 AM
Sometime when working with block designs in Vivado and making a block interface external I get more ports than I'm using. For example, the GMII interface (via EMIO) from a Zynq PS block has the TX_ER signal ,which my HW don't use, and the tx_data bus is 8 bits long when I only use 4-bit MII on HW.
If I leave these ports unconnected (gray) they become assigned to package pins after running implemention. Does the ports connect to the package pins in the same manner as the "wanted" pins?
What is the correct or recommended way to handle this?
12-03-2013 07:53 AM
From the constraints users guide:
"To trim any unused ports from the design, remove the associated constraints. The
Translate (NGDBuild) phase trims these unused pins.
In this example, there are six top-level ports. Only three (clk, A, C) are currently used.
Of the remaining three ports:
• B is kept because it has a Location (LOC) constraint.
• D is kept because it has an Input Output Standard (IOSTANDARD) constraint.
• E is trimmed because it is completely unused and unconstrained."
Remove any constraints that refer to that port, and it will be trimmed....
12-04-2013 05:10 AM
I have now removed the ports from all the xdc files I can find in the project. They are still assigned to pins after running implementation.
Is the constraints users guide (UG625 ?) valid for xdc and Vivado too?
12-04-2013 07:02 AM
Vivado has all new constraints, using the xdc format,
You will need to review the Vivado constraints....
05-12-2017 07:06 AM