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Contributor
Contributor
5,482 Views
Registered: ‎10-08-2013

Create & package IP in 2015.4 selecting VHDL ?

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Hi all,

 

I've just trying to create a custom AXI IP using the "Create and Package IP" tool on vivado 2015.4. Everything seem to be pretty similar as on 2014.x vivado version but the difference I found is that the source files are created in verilog.

 

Is there any way to do the same but with the generated files in VHDL ?

 

Thanks in advance.

Regards.

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Xilinx Employee
Xilinx Employee
10,640 Views
Registered: ‎10-24-2013

Hi @jlesquer

 

What is the target language (in the project settings) set to?

Change it to VHDL and try.

Thanks,Vijay
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Xilinx Employee
Xilinx Employee
10,641 Views
Registered: ‎10-24-2013

Hi @jlesquer

 

What is the target language (in the project settings) set to?

Change it to VHDL and try.

Thanks,Vijay
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

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Contributor
Contributor
5,471 Views
Registered: ‎10-08-2013

Thanks, that solved the problem, I've just updated from 2014 to 2015 version and I was a bit confused with the setup.

Cheers.

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