Create & package IP in 2015.4 selecting VHDL ?

[jlesquer]

Hi all,

I've just trying to create a custom AXI IP using the "Create and Package IP" tool on vivado 2015.4. Everything seem to be pretty similar as on 2014.x vivado version but the difference I found is that the source files are created in verilog.

Is there any way to do the same but with the generated files in VHDL ?

Thanks in advance.

Regards.

[vijayak · Accepted solution]

Hi @jlesquer

What is the target language (in the project settings) set to?

Change it to VHDL and try.

[jlesquer]

Thanks, that solved the problem, I've just updated from 2014 to 2015 version and I was a bit confused with the setup.

Cheers.