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twomack
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Registered: ‎09-02-2012

Creating Basic(?) Custom Logic for the PLB Bus

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So I want to go about doing something which I think should be pretty simple, but I'm not really sure what I should look at to accomplish this.

 

I basically want to have some sort of custom logic on the PLB bus that can intercept writes to certain addresses. For instance, if this monitor logic saw a write accross the bus to the UART module, it would intercept the data and send other data instead--hopefully, within the same clock cycle (Think a simple 2 or 3 state machine with a mux, or something like that.).

 

Anyway, I took a look through the EDK CTT guide, and it seems like the tools provided by XPS for generating custom IP all have formal master/slave interfaces and aren't really meant for what I want to do. Is there anything I'm not aware of that does something more similar to what I want? Or maybe there's a better approach to accomplishing this?

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hgleamon1
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Registered: ‎11-14-2011

If you right-click on the IP in the catalogue, you can choose "Make this IP local". This will place a complete copy of the IP into your project's (or your network repository's) pcores directory. You can then edit as you see fit and add the IP as you usually would for your own pcores.

 

Regards,

 

Howard

 

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"That which we must learn to do, we learn by doing." - Aristotle

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hgleamon1
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Registered: ‎11-14-2011

What you seem to be describing is some sort of Master Snooper, where you can "listen" to the bus and overwrite the data if necessary. I have never heard of one of these in practice.

 

As you have pointed out yourself, the bus structure has either Masters (capable of initiating transactions) or slaves (only capable of receiving transactions). Structures such as PLB have arbitration which means that only one Master can own the bus at any one time. I can't envisage how your proposed Snooper would be able to both be a Slave (i.e. listening on the bus) and then Master the data during a transaction owned by a different Master.

 

The easiest way I can think of for you to achieve your proposal, taking your example of the UART, would be to modify the existing UART interface to have your Snooper built into that peripheral. If you wished to have your Snooper listen to the whole bus for every peripheral, you would need to instantiate a Snooper in EVERY peripheral (but, as what it will do is quite simple, it may not take up so many resources to do this).

 

Regards,

 

Howard

 

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"That which we must learn to do, we learn by doing." - Aristotle
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twomack
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Registered: ‎09-02-2012

Thanks for your input!

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twomack
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Registered: ‎09-02-2012

Is there a way to edit the actual Xilinx VHDL modules (say for example I wanted to edit xps_uartlite.vhd or uartlite_core.vhd)?

 

When I look at them by right-clicking the components in the system assembly view, I can read but not edit the VHDL files. I wrote a small module that I want to put in Xilinx's uart design, but I can't figure out how to edit their files.

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hgleamon1
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5,557 Views
Registered: ‎11-14-2011

If you right-click on the IP in the catalogue, you can choose "Make this IP local". This will place a complete copy of the IP into your project's (or your network repository's) pcores directory. You can then edit as you see fit and add the IP as you usually would for your own pcores.

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle

View solution in original post

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twomack
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Registered: ‎09-02-2012

Thanks again!

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