I wish to develop my own combination of tandem configuration of using the on board QSPI for 1st stage bitstream and loading the driver for my external device(memory) to load the 2nd stage bitstream.
As i wish to use only RTL(PL section) for my first stage bitstream.
1. Load the first stage bitstream on QSPI on power on the FPGA will start executing the first stage bitstream which will start reading the data from my external device and forward the data to ICAPE primitive. Once the ICAPE2 primitive loads this bitstream into the configuration area, i am all good.
1. Is my approach right?
2. I am confused about where does the output of ICAPE2 primitive is connected to, considering the input is from my external device? What i see on vivado is ICAPE2 is a normal port with input, output and clock.