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Contributor
Contributor
2,847 Views
Registered: ‎11-14-2011

DCM_SP (clock multiplier)

Dear sir,

 

I have implemented clock multiplier using DCM_SP library in VHDL using spartan 6 processor and i have multiplied 100mhz clock into 1GHZ its working fine.

 

but my question is how can i implement this method of clock mulitplier in system generator, whether its possible, how?

 

pleaes help me.

Shark
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Scholar
Scholar
2,835 Views
Registered: ‎02-27-2008

Re: DCM_SP (clock multiplier)

s,

 

1 GHz is out of specification.  Not every device will operate that fast, and in fact, most will not.  I am totally amazed that you claim it works in fact.  It probably does not work, you just think it does?

 

Generally, Spartan 6 is not able to have system clock speeds in excess of 250 MHz without exceptionally careful floorplanning, and pipelining (one stage of logic beteween registers).

 

S6 was optimized for low power, not performance.  The Virtex product line is optimized for performance, but none of those support a 1 GHz system clock, either.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Contributor
Contributor
2,825 Views
Registered: ‎11-14-2011

Re: DCM_SP (clock multiplier)

ok sir, how can i use this method in system generator for 250mhz that frequency is ok for implementing higher frequency.

Shark
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