Hi @carlos.sp76
I see below component declaration and instantiations in overcurrent.vhd file
component counter1 is
port(CLK,SET:in std_logic; OUT_SIG:out std_logic);
end component;
component counter2 is
port (CLK,SET: in std_logic; DELAY: in integer range 0
to 31; OUT_SIG: out std_logic);
end component;
counter12: counter2 port map (CLK, SET1, DELAY, S1);
counter:counter1 port map (CLK,SET,S0);
In the counter.vhd I see below
entity counter is
port (
CLK: in std_logic;
SET: in std_logic;
DELAY: in integer range 0 to 31;
OUT_SIG: out std_logic);
end counter;
As you can see there is no entity for counter1,counter2 modules.
If the counter.vhd file corresponds to the counter1,counter2 then make the changes as shown in attached files.
This link has some good information on component instantiation http://web.engr.oregonstate.edu/~traylor/ece474/vhdl_lectures/component_instantiaton.pdf
Thanks,
Deepika.
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