03-30-2016 07:53 PM
03-30-2016 08:43 PM
Please check the following threads where similar topic is discussed.
03-30-2016 11:37 PM
Can you upload the overcurrent.vhd file here? or show us the instantiation of counter1,counter2
This can happen when there is a library mismatch.
03-31-2016 07:39 AM
03-31-2016 07:49 AM
Your top level module overcurrent.vhd is instantiating two modules counter1,counter2 however the only other file you are adding is counter module (counter.v) hence the error, please correct this.
03-31-2016 09:42 AM - edited 03-31-2016 09:45 AM
I see below component declaration and instantiations in overcurrent.vhd file
component counter1 is
port(CLK,SET:in std_logic; OUT_SIG:out std_logic);
component counter2 is
port (CLK,SET: in std_logic; DELAY: in integer range 0
to 31; OUT_SIG: out std_logic);
counter12: counter2 port map (CLK, SET1, DELAY, S1);
counter:counter1 port map (CLK,SET,S0);
In the counter.vhd I see below
entity counter is
CLK: in std_logic;
SET: in std_logic;
DELAY: in integer range 0 to 31;
OUT_SIG: out std_logic);
As you can see there is no entity for counter1,counter2 modules.
If the counter.vhd file corresponds to the counter1,counter2 then make the changes as shown in attached files.
This link has some good information on component instantiation http://web.engr.oregonstate.edu/~traylor/ece474/vhdl_lectures/component_instantiaton.pdf
03-31-2016 09:48 AM
Also ensure that you are properly connecting input and output ports properly.