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Visitor carlos.sp76
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10,020 Views
Registered: ‎02-25-2016

DRC 23-20_Rule Violation (INBB-3)

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Hi,

 

I have two files VHDL code being overcurrent.vhd the main entities depends on counter counter1 and counter2-counter12-counter.vhd file, the 2015.4.2 Vivado.
 
When I run the synthesis, only the overcurrent.vhd file is executed. What is the procedure to create a dependency on counter.vhd file in overcurrent.vhd?
 
Message:
[DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'counter' of type 'counter/counter1' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.
 
Thanks!
 
Regards,
 
Carlos
DRC 23-20_Rule Violation.jpg
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Visitor carlos.sp76
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Registered: ‎02-25-2016

Re: DRC 23-20_Rule Violation (INBB-3)

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Hi Deepika,
 
Thank you, for the information and for your help.

 

Checked inputs and outputs as well.

 

Greetings!
 
Carlos
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-24-2013

Re: DRC 23-20_Rule Violation (INBB-3)

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Hi @carlos.sp76

Please check the following threads where similar topic is discussed.

https://forums.xilinx.com/t5/Implementation/ERROR-DRC-23-20-Rule-violation-INBB-3-Black-Box-Instances/td-p/680823

https://forums.xilinx.com/t5/Welcome-Join/DRC-23-20-Rule-violation-INBB-3-Black-Box-Instances/td-p/686670

Thanks,Vijay
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Xilinx Employee
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Registered: ‎09-20-2012

Re: DRC 23-20_Rule Violation (INBB-3)

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Hi @carlos.sp76

 

Can you upload the overcurrent.vhd file here? or show us the instantiation of counter1,counter2

 

This can happen when there is a library mismatch.

Thanks,
Deepika.
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Visitor carlos.sp76
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Registered: ‎02-25-2016

Re: DRC 23-20_Rule Violation (INBB-3)

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Hi Deepika,

 

Thank you very much for your reply, please find attached the file overcurrent and the dependency file counter.vhd.

 

Greetings and thank you very much!
 
Carlos Magno
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Xilinx Employee
Xilinx Employee
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Registered: ‎09-20-2012

Re: DRC 23-20_Rule Violation (INBB-3)

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Hi @carlos.sp76

 

Your top level module overcurrent.vhd is instantiating two modules counter1,counter2 however the only other file you are adding is counter module (counter.v) hence the error, please correct this.

Thanks,
Deepika.
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Visitor carlos.sp76
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Re: DRC 23-20_Rule Violation (INBB-3)

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Hi Deepika.,

 

I don't know what should I do with the counter.vhd file, can you explain?

 

Thanks,

 

Carlos

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Xilinx Employee
Xilinx Employee
9,938 Views
Registered: ‎09-20-2012

Re: DRC 23-20_Rule Violation (INBB-3)

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Hi @carlos.sp76

 

I see below component declaration and instantiations in overcurrent.vhd file

 

component counter1 is
port(CLK,SET:in std_logic; OUT_SIG:out std_logic);
end component;
component counter2 is
port (CLK,SET: in std_logic; DELAY: in integer range 0
to 31; OUT_SIG: out std_logic);
end component;

 

 counter12: counter2 port map (CLK, SET1, DELAY, S1);

 counter:counter1 port map (CLK,SET,S0);

 

In the counter.vhd I see below

 

entity counter is
port (
CLK: in std_logic;
SET: in std_logic;
DELAY: in integer range 0 to 31;
OUT_SIG: out std_logic);
end counter;

 

As you can see there is no entity for counter1,counter2 modules. 

If the counter.vhd file corresponds to the counter1,counter2 then make the changes as shown in attached files.

 

This link has some good information on component instantiation http://web.engr.oregonstate.edu/~traylor/ece474/vhdl_lectures/component_instantiaton.pdf

 

Thanks,
Deepika.
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Xilinx Employee
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Registered: ‎09-20-2012

Re: DRC 23-20_Rule Violation (INBB-3)

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Hi @carlos.sp76

Also ensure that you are properly connecting input and output ports properly.

Thanks,
Deepika.
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Visitor carlos.sp76
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Registered: ‎02-25-2016

Re: DRC 23-20_Rule Violation (INBB-3)

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Hi Deepika,
 
Thank you, for the information and for your help.

 

Checked inputs and outputs as well.

 

Greetings!
 
Carlos
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