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msh
Voyager
Voyager
5,319 Views
Registered: ‎10-31-2016

[DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop

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hi, 

 

I am getting an error, I donot understand whats wrong in the simple code. It will help me further ti understand more about VHDL: 
[DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop - 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. To allow bitstream creation for designs with combinatorial logic loops (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. design_1_i/TDC_EvaluationSignal_0/U0/StopSignal_INST_0.

Output goes to LVDS buffer. And ref clock is run from PS.

Code: 

 

entity TDC_EvaluationSignal is
Port ( RefClk : in STD_LOGIC;
StopSignal : out STD_LOGIC;
TDCrefClk : out STD_LOGIC);
end TDC_EvaluationSignal;
architecture Behavioral of TDC_EvaluationSignal is
signal StopSignalReg: STD_LOGIC := '0'; 
signal TDCrefClkReg: STD_LOGIC := '0';
signal counterReg: integer := 0; 
begin
Generateclock : process (RefClk) begin
if (RefClk= '1') then 
TDCrefClkReg <= not TDCrefClkReg; 
counterReg <= counterReg +1; 
end if; 
if (counterReg >= 1 and RefClk= '1') then 
counterReg <= 0;
StopSignalReg <= not StopSignalReg;
else 
StopSignalReg <= '0'; 
end if;
end process; 
StopSignal <= StopSignalReg;
TDCrefClk <= TDCrefClkReg;
end Behavioral;

Capture.PNG

Thank you 

Best regards

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1 Solution

Accepted Solutions
syedz
Moderator
Moderator
9,674 Views
Registered: ‎01-16-2013

@msh,

 

A combinational loop is combinational logic that feeds back to itself without a register. The simplest example is an inverter whose output feeds back to the input creating an oscillator.

 

I was able to replicate the same DRC with the shared RTL code. You need to modify your code to avoid the Loop back.

Capture.JPG

 

--Syed

 

 

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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View solution in original post

2 Replies
syedz
Moderator
Moderator
9,675 Views
Registered: ‎01-16-2013

@msh,

 

A combinational loop is combinational logic that feeds back to itself without a register. The simplest example is an inverter whose output feeds back to the input creating an oscillator.

 

I was able to replicate the same DRC with the shared RTL code. You need to modify your code to avoid the Loop back.

Capture.JPG

 

--Syed

 

 

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

gszakacs
Professor
Professor
5,288 Views
Registered: ‎08-14-2007

Your process looks like it was written for simulation.  Here you have for example:

 

Generateclock : process (RefClk) begin
if (RefClk= '1') then

 

For simulation, that means that the process will only run when RefClk changes.  For synthesis, the process sensitivity list is essentially ignored, meaning that you need to explicitly tell the compiler you want an action to happen only on the clock edge, for example:

 

Generateclock : process (RefClk) begin
if (RefClk'event and RefClk= '1') then

 

Without the explicit requirement for edge detection, the process is taken to be combinatorial and then the next statement:

 

TDCrefClkReg <= not TDCrefClkReg;

 

forms a combinatorial loop, since it runs continuously while RefClk is high.

-- Gabor