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Observer
Observer
3,089 Views
Registered: ‎01-05-2016

[DRC 23-20] Rule violation

Hi 

I realized a basic microblaze design with vivado 2015.4 and I generated the bitstream successfully, and then I created a custum IP which is a HW timer and I connect it via AXI stream interface with the basic design of microblaze.

Synthesising the design completed successfully but when I run the implementation this error bursts:

 

    • [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'mb_design_1_i/my_timmer_0/U0/u1' of type 'mb_design_1_i/my_timmer_0/U0/u1/Timer' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

What should I do please ??

 

 

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Xilinx Employee
Xilinx Employee
3,075 Views
Registered: ‎07-11-2011

@s_zo

 

It looks your custom IP instance is treated as black box, have you included its .xci?

Could be something wrong with the flow or connectivity.

 

Please check relavant discussions and cross check against yours and see if it helps

 

https://forums.xilinx.com/t5/Implementation/ERROR-DRC-23-20-Rule-violation-INBB-3-Black-Box-Instances/td-p/680823

 

https://forums.xilinx.com/t5/Implementation/INBB-3-The-contents-of-this-cell-must-be-deifned-for-opt-design/td-p/672542

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Observer
Observer
3,035 Views
Registered: ‎01-05-2016

Hi thank you for your reply, but where can I find the file .xci and where should I include it ??

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