12-20-2016 04:44 AM - edited 12-20-2016 04:49 AM
I am trying to use 200 MHz differential system clock to generate 200 MHz clock and use this clock to debug other clocks(148.5 Mhz, 148.3 Mhz, 27Mhz etc.) in the design.
This is how I proceed:
#200MHz system clock option board
set_property PACKAGE_PIN AD12 [get_ports sys_clk_p]
set_property PACKAGE_PIN AD11 [get_ports sys_clk_n]
set_property IOSTANDARD LVDS [get_ports sys_clk_p]
set_property IOSTANDARD LVDS [get_ports sys_clk_n]
generating single ended using IBUF:
// sys clock to test
//just to test
always @ (posedge sys_clk)
test_x <= test_y;
now I want to use sys_clk to debug another clocks in the design.
but sys_clock didn't appear in the debug(see attachment) core clock selection. What should has to be done ?
There is no error during bit generation.
12-20-2016 08:54 PM
First of all when you are debugging a signal of 148.5MHz then the clock connected to ILA should be atleast twice of 148.5MHz.
After doing setup debug and saving the project constraints will be saved to XDC file. There change the below commands according to your clock net requirement:
connect_debug_port u_ila_0/clk [get_nets [list CLK_BUFG]]
connect_debug_port dbg_hub/clk [get_nets CLK_BUFG]
12-22-2016 09:51 PM
Were the suggestions provided helpful?