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Visitor melpinfpga94
Visitor
5,877 Views
Registered: ‎03-04-2016

Delay Element Error

This is the testbench code of the schematic design. The error is as follows :

I have defined the X_REG as array vector of vect_12x30 but in the test bench it is giving it a std_logic_vector of 0 to 30. Now its a port of 12 bits giving out samples (30 samples ) ie. It is an array.

Please help me out

 

 


library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity DelayElement is
   port ( F_CLK_4MHz       : in    std_logic;
          F_IL             : in    std_logic_vector (1 downto 0);
          F_RESET          : in    std_logic;
          F_ADC_CLK        : out   std_logic;
          F_ADC_CONVST_BAR : out   std_logic;
          F_ADC_CS_BAR     : out   std_logic;
          F_ADC_RD_BAR     : out   std_logic;
          F_ADC_WR_BAR     : out   std_logic;
          F_CS1_BAR        : out   std_logic;
          F_CS2_BAR        : out   std_logic;
          F_CS3_BAR        : out   std_logic;
          F_CS4_BAR        : out   std_logic;
          F_DAC_D          : out   std_logic_vector (11 downto 0);
          F_WE_BAR         : out   std_logic;
          OUT_DONE         : out   std_logic;
          F_ADC_D          : inout std_logic_vector (11 downto 0));
end DelayElement;

architecture BEHAVIORAL of DelayElement is
   signal XLXN_3           : std_logic;
   signal XLXN_5           : std_logic_vector (0 to 29);
   signal XLXN_6           : std_logic_vector (11 downto 0);
   component ADC_DAC_interface
      port ( F_RESET          : in    std_logic;
             F_CLK_4MHz       : in    std_logic;
             F_IL             : in    std_logic_vector (1 downto 0);
             DELAY_IN         : in    std_logic_vector (11 downto 0);
             F_ADC_D          : inout std_logic_vector (11 downto 0);
             F_ADC_CLK        : out   std_logic;
             F_ADC_CS_BAR     : out   std_logic;
             F_ADC_CONVST_BAR : out   std_logic;
             F_ADC_WR_BAR     : out   std_logic;
             SAMPLE_HOGAYA    : out   std_logic;
             F_ADC_RD_BAR     : out   std_logic;
             F_WE_BAR         : out   std_logic;
             F_CS1_BAR        : out   std_logic;
             F_CS2_BAR        : out   std_logic;
             F_CS3_BAR        : out   std_logic;
             F_CS4_BAR        : out   std_logic;
             F_DAC_D          : out   std_logic_vector (11 downto 0));
   end component;
   
   component DELAY_FILTER
      port ( F_CLK_4MHz  : in    std_logic;
             F_RESET     : in    std_logic;
             SAMPLE_DONE : in    std_logic;
             X_REG       : in    std_logic_vector (0 to 29); --This is a vector but it is given as std_logic_vector.Why so?
             OUT_DONE    : out   std_logic;
             Y           : out   std_logic_vector (11 downto 0));
   end component;
   
   component SHIFT_REGISTER
      port ( F_CLK_4MHz : in    std_logic;
             F_RESET    : in    std_logic;
             D          : in    std_logic_vector (11 downto 0);
             VEC        : out   std_logic_vector (0 to 29));     --This is a vector but it is given as std_logic_vector.Why so?
   end component;
   
begin
   XLXI_1 : ADC_DAC_interface
      port map (DELAY_IN(11 downto 0)=>XLXN_6(11 downto 0),
                F_CLK_4MHz=>F_CLK_4MHz,
                F_IL(1 downto 0)=>F_IL(1 downto 0),
                F_RESET=>F_RESET,
                F_ADC_CLK=>F_ADC_CLK,
                F_ADC_CONVST_BAR=>F_ADC_CONVST_BAR,
                F_ADC_CS_BAR=>F_ADC_CS_BAR,
                F_ADC_RD_BAR=>F_ADC_RD_BAR,
                F_ADC_WR_BAR=>F_ADC_WR_BAR,
                F_CS1_BAR=>F_CS1_BAR,
                F_CS2_BAR=>F_CS2_BAR,
                F_CS3_BAR=>F_CS3_BAR,
                F_CS4_BAR=>F_CS4_BAR,
                F_DAC_D(11 downto 0)=>F_DAC_D(11 downto 0),
                F_WE_BAR=>F_WE_BAR,
                SAMPLE_HOGAYA=>XLXN_3,
                F_ADC_D(11 downto 0)=>F_ADC_D(11 downto 0));
   
   XLXI_2 : DELAY_FILTER
      port map (F_CLK_4MHz=>F_CLK_4MHz,
                F_RESET=>F_RESET,
                SAMPLE_DONE=>XLXN_3,
                X_REG(0 to 29)=>XLXN_5(0 to 29),
                OUT_DONE=>OUT_DONE,
                Y(11 downto 0)=>XLXN_6(11 downto 0));
   
   XLXI_3 : SHIFT_REGISTER
      port map (D(11 downto 0)=>F_ADC_D(11 downto 0),
                F_CLK_4MHz=>F_CLK_4MHz,
                F_RESET=>F_RESET,
                VEC(0 to 29)=>XLXN_5(0 to 29));
   
end BEHAVIORAL;

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2 Replies
Moderator
Moderator
5,873 Views
Registered: ‎07-01-2015

Re: Delay Element Error

Hi @melpinfpga94,

 

Please go through
http://www.xilinx.com/support/answers/32981.html

http://www.xilinx.com/support/answers/33877.html

 

Thanks,
Arpan

Thanks,
Arpan
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Visitor melpinfpga94
Visitor
5,853 Views
Registered: ‎03-04-2016

Re: Delay Element Error

X_REG and VEC are vector types . I have also defined them in my CONF file(Where i have declared all components) as follows :

 

type vect_12x30 is array (0 to 29) of std_logic_vector(11 downto 0);

 

According to your support answers , they have fiddled with the type of data (bit vector is changed back to std_logic_vec) which i don't want to.

Please help

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