Software: Xilinx ISE 13.1, ChipScope Pro (de-bugging) Language: Verilog HDL FPGA: Xilinx Virtex-6 LX365T
Description: I have a design (Verilog RTL) with 42 modules. Overall consumption of my RTL design is 54% of Virtex-6 FPGA. Clock Constraint is 60MHz. Inside the design I am using DCM for to generate the TWO Clock “clk_0x” (60MHz) and “clk_2x” (120MHz), as per my design requirement. I have generated a bitstream ( design_test.bit ) for my whole design and test it real time functionality on my custom board. Its verified and hardware results are matched with expected results.
Question: The Issue is when I run the test with bitstream ( design_test.bit ) 100 times with same inputs then from run 5~6 time my result surprisingly goes wrong badly. 94 times my results are consistent and matched. It looks my result goes towards saturation level. I apply rest to my design at the start of every Run.
Need your suggestion, why my bitstream ( design_test.bit ) behaving like this. I also done implementation process through PlanAhead Strategies and SmartXplorer’s Cost Table but no improvement yet.