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Visitor
Visitor
3,551 Views
Registered: ‎01-26-2016

Does the RTL from vivado hls can be synthesis by Design Compiler ?

 HI 

 I have a question for vivado hls.

 Is the  RTL gerenated from vivado hls  onyl for xilinx FPGA ?

 Can we use it to be synthesied on Design Compiler?

Thanks

 

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Scholar
Scholar
3,530 Views
Registered: ‎06-05-2013

Re: Does the RTL from vivado hls can be synthesis by Design Compiler ?

@abayson Only For Xilinx Fpga Families.

-Pratham

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Scholar
Scholar
3,519 Views
Registered: ‎09-05-2011

Re: Does the RTL from vivado hls can be synthesis by Design Compiler ?

When creating a new project in HLS, you specify the target device on which you will be using the resulting RTL. Therefore, in general, the RTL is to be used on Xilinx FPGA.
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Visitor
Visitor
3,513 Views
Registered: ‎01-26-2016

Re: Does the RTL from vivado hls can be synthesis by Design Compiler ?

 Thanks for your answer

 

 That is my understand

  If you only use simple logic in the source C code, the result RTL can synthesized on Design Compiler.

  I try to write one Matrix Multiplication on C and put the RTL from vivado hls into synthesized. It is successful.

  However, if your C is more complex, the RTL need use some specifical cell/logic which on FPGA.

  This RTL can not be  synthesized.

  Please correct me if my understand is wrong. 

 

  Thanks

 

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Advisor
Advisor
3,483 Views
Registered: ‎04-26-2015

Re: Does the RTL from vivado hls can be synthesis by Design Compiler ?

As far as I know, it's largely generic Verilog/VHDL code. That includes RAMs and DSP slices; HLS just puts arrays or multiply symbols in the code and lets the main synthesis tool replace them with appropriate equivalents. The exceptions are obviously stuff included from Xilinx libraries, and AXI interfaces (HLS just leaves a tag that tells the main synthesis tool to put an AXI interface there; this allows the synthesis tool to customise the interface). Obviously the HLS resource usage estimates may be totally wrong if you use a different device, and it's likely that Xilinx's own synthesis tool is somewhat optimised for the (horrible) Verilog/VHDL that HLS outputs.

 

As far as I can remember, the license would allow you to use Design Compiler if you're building this for a Xilinx device. If you're aiming at an Altera device, then you're breaking the license agreement.

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Xilinx Employee
Xilinx Employee
3,421 Views
Registered: ‎03-22-2011

Re: Does the RTL from vivado hls can be synthesis by Design Compiler ?

The license agreement you accepted when you installed the software specifically prohits you from using the RTL for anything other than a Xilinx FGPA.

 

 

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