01-26-2016 06:20 PM
I have a question for vivado hls.
Is the RTL gerenated from vivado hls onyl for xilinx FPGA ?
Can we use it to be synthesied on Design Compiler?
01-26-2016 07:57 PM
@abayson Only For Xilinx Fpga Families.
01-26-2016 09:11 PM
01-26-2016 09:53 PM
Thanks for your answer
That is my understand
If you only use simple logic in the source C code, the result RTL can synthesized on Design Compiler.
I try to write one Matrix Multiplication on C and put the RTL from vivado hls into synthesized. It is successful.
However, if your C is more complex, the RTL need use some specifical cell/logic which on FPGA.
This RTL can not be synthesized.
Please correct me if my understand is wrong.
01-27-2016 01:49 AM
As far as I know, it's largely generic Verilog/VHDL code. That includes RAMs and DSP slices; HLS just puts arrays or multiply symbols in the code and lets the main synthesis tool replace them with appropriate equivalents. The exceptions are obviously stuff included from Xilinx libraries, and AXI interfaces (HLS just leaves a tag that tells the main synthesis tool to put an AXI interface there; this allows the synthesis tool to customise the interface). Obviously the HLS resource usage estimates may be totally wrong if you use a different device, and it's likely that Xilinx's own synthesis tool is somewhat optimised for the (horrible) Verilog/VHDL that HLS outputs.
As far as I can remember, the license would allow you to use Design Compiler if you're building this for a Xilinx device. If you're aiming at an Altera device, then you're breaking the license agreement.
01-27-2016 10:04 PM
The license agreement you accepted when you installed the software specifically prohits you from using the RTL for anything other than a Xilinx FGPA.