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davide_marano
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Registered: ‎03-08-2017

Done LED does not keep off upon constraint

Dear Community,

 

my team and I have been struggling with a problem concerning the configuration of the done pin of our FPGA.

 

As we need to keep the done LED off after downloading the .bit file into the FPGA (or the .mcs file into the flash memory), we have included the following constraint in VIVADO:

 

set_property BITSTREAM.STARTUP.DONE_CYCLE Keep [current_design]

 

We have always succeeded in keeping the LED off through the above constraint, until we have modified the original design by adding a QUAD-SPI module to communicate with the external flash memory. It seems as if the insertion of the new block disabled the reading of the constraint, since the done LED in the board turns back on despite the constraint.

 

The project is implemented in VIVADO 2015.2 System Edition and the target FPGA is an Artix 7.

 

Does anyone have any suggestion on how to keep the LED off? Is there any additional constraints or configuration settings to apply? Many thanks in advance.

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austin
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Registered: ‎02-27-2008

d,

 

Check to order of the constraints.  It may be the IP causes its constraints to be prioritized first, thereby negating the latter one.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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davide_marano
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Registered: ‎03-08-2017

Dear austin,

 

thanks for your suggestion, but unfortunately the LED keeps turning on.

The strange point is that the insertion of the new IPs (axi_quad_spi and ext_flash_wrapper in the first attached figure) didn’t involve any additional constraints in the project with respect to the previous version, since the five related pins (flash_d0/d3 and qspi_ic_cs_b) had already been included in the original project where the LED kept off; they were just not connected in the BD but linked out in the top VHDL module, and the associated PACKAGE_PIN and IOSTANDARD constraints below were present all the same:

 

set_property PACKAGE_PIN P21 [get_ports flash_d2]

set_property PACKAGE_PIN R21 [get_ports flash_d3]

set_property PACKAGE_PIN P22 [get_ports flash_d0]

set_property PACKAGE_PIN R22 [get_ports flash_d1]

set_property PACKAGE_PIN T19 [get_ports qspi_ic_cs_b]

 

set_property IOSTANDARD LVCMOS33 [get_ports flash_d2]

set_property IOSTANDARD LVCMOS33 [get_ports flash_d3]

set_property IOSTANDARD LVCMOS33 [get_ports flash_d0]

set_property IOSTANDARD LVCMOS33 [get_ports flash_d1]

set_property IOSTANDARD LVCMOS33 [get_ports qspi_ic_cs_b]

 

Following your advice, we have searched for priority conditions on the constraints, and tried to isolate the following line:

 

set_property BITSTREAM.STARTUP.DONE_CYCLE Keep [current_design]

 

in a single constraint file at the top of the .xdc file list, but still the LED turned on.

 

Also, we have tried to change the PROCESSING_ORDER property of the constraint file (EARLY, LATE) as in the second attached figure), but we did not even succeed this time in keeping this LED off :-(

 

Any suggestions will be very much appreciated.

 

Many thanks.

QUAD-SPI.jpg
constraint_order.jpg
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austin
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Registered: ‎02-27-2008

IP blocks get their constraints handled first (they are there, look for those xdc files).  You may need to edit them,

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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davide_marano
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Registered: ‎03-08-2017

Dear austin,

 

the 4 xdc files reported in the second figure of the previous post do not comprise any constraints related to IP blocks.

 

In the Compile order tab in VIVADO we have noted some additional constraints, among which some related to the QUAD SPI IP, as in the attached figure. We report below the contents of these files, but they are read-only. The inserted QUAD SPI is a Xilinx native IP, so that the following constraints are automatically generated.

 

…quad_spi_0_0_board

--------------------------------

Empty

 

…quad_spi_0_0

-----------------------

set_false_path -from [get_cells -hierarchical -filter {NAME =~*_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/*rstblk*/*rst_reg_reg[*]}]

set_false_path -to [get_pins -hierarchical -filter {NAME =~*_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/*rstblk*/*PRE}]

set_false_path -to [get_pins -hierarchical -filter {NAME =~*/*rstblk*/*CLR}]

 

## IOB constraints ######&& {$start_up == 1}

set_property IOB true [get_cells -hierarchical -filter {NAME =~*IO*_I_REG}]

 

…quad_spi_0_0_clocks

--------------------------------

set clk_domain_axi_lite [get_clocks -of_objects [get_ports s_axi_aclk]]

                                   set clk_domain_ext_spi_clk [get_clocks -of_objects [get_ports ext_spi_clk]]

# Set max delay on cross clock domain path for Block/Distributed RAM based FIFO

            set_false_path -from [filter [all_fanout -from [get_ports ext_spi_clk] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~*RX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[*]}]

            set_max_delay -from [get_cells -hierarchical -filter {NAME =~*RX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_reg[*]}] -to [get_cells -hierarchical -filter {NAME =~*RX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].wr_stg_inst/Q_reg_reg[*]}] -datapath_only [get_property -min PERIOD $clk_domain_axi_lite]

            set_max_delay -from [get_cells -hierarchical -filter {NAME =~*RX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_reg[*]}] -to [get_cells -hierarchical -filter {NAME =~*RX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].rd_stg_inst/Q_reg_reg[*]}] -datapath_only [get_property -min PERIOD $clk_domain_ext_spi_clk]

 

            set_false_path -from [filter [all_fanout -from [get_ports s_axi_aclk] -flat -endpoints_only] {IS_LEAF}] -to [get_cells -hierarchical -filter {NAME =~*TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm/gpr1.dout_i_reg[*]}]

                                   set_max_delay -from [get_cells -hierarchical -filter {NAME =~*TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc_reg[*]}] -to [get_cells -hierarchical -filter {NAME =~*TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].wr_stg_inst/Q_reg_reg[*]}] -datapath_only [get_property -min PERIOD $clk_domain_ext_spi_clk]

            set_max_delay -from [get_cells -hierarchical -filter {NAME =~*TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc_reg[*]}] -to [get_cells -hierarchical -filter {NAME =~*TX_FIFO_II/USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gsync_stage[*].rd_stg_inst/Q_reg_reg[*]}] -datapath_only [get_property -min PERIOD $clk_domain_axi_lite]

 

We also report the compile order log.

 

We are still searching for a possible solution to keep the DONE LED off at start up.

constraints.jpg
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austin
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Registered: ‎02-27-2008

OK,

 

I am out of ideas.  Perhaps someone else has an answer?  If you cannot edit the IP constraints, and they always are asserted first, then perhaps this is a feature collision (can't get there from here)?

Austin Lesea
Principal Engineer
Xilinx San Jose
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