08-10-2016 08:42 PM
Please clarify on following doubts regarding AXI memory mapped to PCIe.
1. What are the configuration done through S_AXI_CTL interface?
2. Can more than one master access PCIe endpoint by connecting more than one AXI masters through axi_interconnect block to S_AXI port of AXI PCIe?
08-11-2016 12:51 PM
08-11-2016 10:01 PM - edited 08-11-2016 10:04 PM
Thanks for the clarification
for SAXI_CTL , I understand BAR address translation is done by AXI PCIE ip and not done outside. Isn't it?