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Observer
Observer
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Registered: ‎01-05-2016

[Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Hi 

I'm trying to run FreeRTOS Operating System on Microblaze soft core in Zynq ZC702 board, I'm trying to generate a bitstream for my design I got this error 

 

  • [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 2 out of 119 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: uart_rtl_rxd, uart_rtl_txd.

What should I do please ??

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Xilinx Employee
Xilinx Employee
14,300 Views
Registered: ‎09-20-2012

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Hi @s_zo

 

Can you attach your TCL file here? What all commands you have in the TCL file? Just have the below command

 

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
8,728 Views
Registered: ‎09-20-2012

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Hi @s_zo

 

You have not specified LOC constraint for the below ports, hence you are seeing this error.

 

uart_rtl_rxd,

uart_rtl_txd

 

Please assign the LOC constraint.

 

If you want to override the error without assiging LOC constraint then check this article http://www.xilinx.com/support/answers/56354.html

 

Thanks,

Deepika.

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎01-05-2016

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Hi Deepika,

 

I added "set_property SEVERITY {Warning} [get_drc_checks UCIO-1]" command to Tcl script as mentionned in the error  message to down grad this error to a warning and I try to generate the bitstream but this error still exist.

 

What should I do please.

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Xilinx Employee
Xilinx Employee
8,711 Views
Registered: ‎09-20-2012

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Hi @s_zo

 

source the tcl file in tcl.pre of bitstream settings

 

Capture.PNG

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎01-05-2016

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Hi Deepika

 

Sorry but I can't source the tcl file in tcl.pre of bitstream settings, Why I dont have the label that allow me to source files ? 

 

Bitstream_settings.png

 

 

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Xilinx Employee
Xilinx Employee
8,699 Views
Registered: ‎09-20-2012

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Hi @s_zo

 

Try running the below command from tcl console

 

set_property STEPS.WRITE_BITSTREAM.TCL.PRE {<file_path>\test.tcl} [get_runs impl_1]

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎01-05-2016

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Hi Deepika

 

I added the command that you mentionned and I get this 

 

Bitstream_settings.png

 

What should I do ?

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Xilinx Employee
Xilinx Employee
8,679 Views
Registered: ‎09-20-2012

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Hi @s_zo

 

You need to replace the <file_path> with path to the TCL file and test.tcl with the name of TCL file.

 

Create a TCL file and copy the command mentioned in the AR to that TCL file in case if you have not done that yet,

 

Thanks,

Deepika. 

Thanks,
Deepika.
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Observer
Observer
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Registered: ‎01-05-2016

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Hi Deepika,

 

I created a Tcl file and I add the command (set_property SEVERITY {Warning} [get_drc_checks UCIO-1]) at the end of this file and I source it , and I regenerate the bitstream, those Errors burst:

 

  • [runtcl 1] ERROR: [Vivado 12-172] File or Directory 'C:/Users/Sonia/Desktop/FreeRTOS/MicroBkaze_FreeRTOS/MicroBaze_FreeRTOS/mb_design_1/mb_design_1.runs/impl_1/mb_design_1.srcs/sources_1/bd/mb_design_1/mb_design_1.bd' does not exist

 

  • [runtcl 1] sourcing script C:/Users/Sonia/Desktop/FreeRTOS/MicroBkaze_FreeRTOS/MicroBaze_FreeRTOS/mb_design_1/Error_bitstream.tcl failed

what should I do please?

 

 

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Xilinx Employee
Xilinx Employee
14,301 Views
Registered: ‎09-20-2012

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Hi @s_zo

 

Can you attach your TCL file here? What all commands you have in the TCL file? Just have the below command

 

set_property SEVERITY {Warning} [get_drc_checks UCIO-1]

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
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Moderator
Moderator
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Registered: ‎06-24-2015

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Hi @s_zo,

 

Use this file as pre.tcl file, in the manner mentioned by Deepika.

 

Thanks,
Nupur
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Moderator
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Registered: ‎02-16-2010

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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Alternatively, you can also add the following constraint in your top level .xdc file.
set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]

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Observer
Observer
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Registered: ‎01-05-2016

Re: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port

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finally, I generated the bitstream :)

Thanks 

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