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naveengk14
Explorer
Explorer
3,612 Views
Registered: ‎09-16-2013

EDIF File

How to generate EDIF file in Vivado ?

How to call the EDIF file ?

Thanks
Naveen G K
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6 Replies
arpansur
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Registered: ‎07-01-2015

Hi @naveengk14,

 

Open synthesized design.

 Use Tcl command write_edif <top module name>.edf

 

You can use it in post_synth project or you can include in design sources with a stub.

 

Thanks,
Arpan
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naveengk14
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Registered: ‎09-16-2013

Hi,

 

what is the command to call the edif file in TCL script.

Thanks
Naveen G K
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syedz
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Registered: ‎01-16-2013

@naveengk14,

 

read_edif

Check page number 986 in below user guide:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_3/ug835-vivado-tcl-commands.pdf

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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arpansur
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Registered: ‎07-01-2015

Hi @naveengk14,

 

What do you mean by calling the EDIF files?

Is it adding EDIF as source file to project or using EDIF in non project mode?

You can use add_files or read_edif as suggested by @syedz.

Please go through page-58 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_3/ug835-vivado-tcl-commands.pdf for info on add_files

Thanks,
Arpan
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saradapr
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Registered: ‎10-14-2015

Hi @naveengk14,

 

Please check similar post may help.

https://forums.xilinx.com/t5/7-Series-FPGAs/how-to-use-a-edif-file-in-vivado/td-p/561686

 

Thanks,

Sarada

 

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arpansur
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Registered: ‎07-01-2015

Hi @naveengk14,

 

Were the suggestions provided helpful?

Thanks,
Arpan
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