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Visitor harsha216
Visitor
5,406 Views
Registered: ‎11-03-2015

ERROR: [Common 17-70] Application Exception: Failed to stitch checkpoint 'mem.dcp' at cell 'I_ram'.

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Hi I have generated block rams for my design. The synthesis was complete without any errors.

But when I try to open the synthesized design, I get the following error:

ERROR: [Common 17-70] Application Exception: Failed to stitch checkpoint 'mem.dcp' at cell 'I_ram'.

 

I am not able to see the synthesized design due to this error.

 

What am I missing?

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Moderator
Moderator
9,954 Views
Registered: ‎01-16-2013

Re: ERROR: [Common 17-70] Application Exception: Failed to stitch checkpoint 'mem.dcp' at cell 'I_ram'.

Jump to solution

@harsha216

 

This error message is issued when:

  • an IP core in the design is synthesized as an out-of-context (OOC) module and 
  • the synthesized OOC for the IP core results in an empty dcp (Synthesis removes all logic when synthesizing the files delivered for the IP core).

 When Vivado is trying to open the design it is unable to handle/integrate the empty dcp so it fails with the above error.

Workaround:

  1. Select the IP instance in the hierarchy view and unset out-of-context module by right clicking on it.
  2. Now use the IP catalog to create the IP with the same name
  3. Generate the IP
  4. Add the IPname_stub.v file to the project available in the IP location
  5. Remove the already added IPname.v file from the project
  6. Now Synthesis and implement the design.

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
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1 Reply
Moderator
Moderator
9,955 Views
Registered: ‎01-16-2013

Re: ERROR: [Common 17-70] Application Exception: Failed to stitch checkpoint 'mem.dcp' at cell 'I_ram'.

Jump to solution

@harsha216

 

This error message is issued when:

  • an IP core in the design is synthesized as an out-of-context (OOC) module and 
  • the synthesized OOC for the IP core results in an empty dcp (Synthesis removes all logic when synthesizing the files delivered for the IP core).

 When Vivado is trying to open the design it is unable to handle/integrate the empty dcp so it fails with the above error.

Workaround:

  1. Select the IP instance in the hierarchy view and unset out-of-context module by right clicking on it.
  2. Now use the IP catalog to create the IP with the same name
  3. Generate the IP
  4. Add the IPname_stub.v file to the project available in the IP location
  5. Remove the already added IPname.v file from the project
  6. Now Synthesis and implement the design.

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos