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Visitor
Visitor
5,228 Views
Registered: ‎07-28-2016

EXPORTING DESIGN FILES FROM VIVADO 2014.3 TO SYSTEM GENERATOR

Hi, I have created a hardware platform on Vivado , generated bitstream and implemented on SDR (consist of ZYNQ SoC). Now i want to implement the same in System Generator using the HDL files(verilog) generated by Vivado. Is it any method by which i can directly export all the design files from Vivado to System Generator. Thank you Ranjeeth
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Xilinx Employee
Xilinx Employee
5,224 Views
Registered: ‎08-01-2008

Re: EXPORTING DESIGN FILES FROM VIVADO 2014.3 TO SYSTEM GENERATOR

You can do it through black box
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug897-vivado-sysgen-user.pdf

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/sysgen_user.pdf
Thanks and Regards
Balkrishan
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Visitor
Visitor
5,191 Views
Registered: ‎07-28-2016

Re: EXPORTING DESIGN FILES FROM VIVADO 2014.3 TO SYSTEM GENERATOR

Hello Balkrishan,

 

My design file contains 28 IP.

Each IP contains more than 10  vivado generated HDL files. So total more than 300 HDL files are there.

So shall i create black box for each of these codes?

 

Thank You

 

Ranjeeth

 

hdl_vivado_generated_files.png
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Visitor
Visitor
3,240 Views
Registered: ‎12-23-2016

Re: EXPORTING DESIGN FILES FROM VIVADO 2014.3 TO SYSTEM GENERATOR

Good question Ranjeeth. Did you found an answer or a solution because I am facing the same situation.
Thank you
Ahmed

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