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Explorer
Posts: 184
Registered: ‎04-11-2016
Accepted Solution

Error: [Labtools 27-3165] End of startup status: LOW

[ Edited ]

Hi, 

I read already some info about it:

https://forums.xilinx.com/t5/7-Series-FPGAs/JTAG-without-PUDC-B/td-p/634728

but it not seems to be helpful.

 

I am trying to load .bit file on a custom FPGA(xc7k325) board but getting error as in attachment.

 

I did as mentioned in the above link:

"PUDC_B must be tied either directly, or via a ≤ 1 kΩ to VCCO_14 or GND." but it didn't work.

 

surprising to me when I load just simple program (like led blinking) it works but with my program it shows the error.  is there any other reason for this error?

Because i have taken a xilinx reference design which is already working with kc705 evaluation board.

https://www.xilinx.com/support/documentation/application_notes/xapp1199-smpte2022-56-over-ip.pdf

 

only thing I changed here is I mapped the pins as per custom board. All other things is same as evaluation board.

 

Is there any additional setting needed in project setting during bitstream generation.

 

 

2.jpg

Accepted Solutions
Explorer
Posts: 184
Registered: ‎04-11-2016

Re: Error: [Labtools 27-3165] End of startup status: LOW

[ Edited ]

Hi,
thanks sudden voltage drop was the problem.

View solution in original post


All Replies
Instructor
Posts: 9,048
Registered: ‎08-14-2007

Re: Error: [Labtools 27-3165] End of startup status: LOW

It's possible that the project causes the FPGA to draw more power than your board can support, which would then lower Vccint enough to reset the FPGA.  I would suggest scoping on Vccint as close as possible to the FPGA to see if there is a dip in voltage when you configure the part.

 

There are two reasons that the voltage could drop, first that it exceeds the capacity of the supply, and second that the sudden increase in current causes the supply to dip briefly and there is not enough bulk bypass capacitance to hold the voltage above the minimum required to retain configuration.

-- Gabor
Explorer
Posts: 184
Registered: ‎04-11-2016

Re: Error: [Labtools 27-3165] End of startup status: LOW

Hi,

here is further info, if it helps to understand the problem:

Status of configuration register:

 

REGISTER.CONFIG_STATUS 01000000000000000001110100001100
REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR 0
REGISTER.CONFIG_STATUS.BIT01_DECRYPTOR_ENABLE 0
REGISTER.CONFIG_STATUS.BIT02_PLL_LOCK_STATUS 1
REGISTER.CONFIG_STATUS.BIT03_DCI_MATCH_STATUS 1
REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS 0
REGISTER.CONFIG_STATUS.BIT05_GTS_CFG_B_STATUS 0
REGISTER.CONFIG_STATUS.BIT06_GWE_STATUS 0
REGISTER.CONFIG_STATUS.BIT07_GHIGH_STATUS 0
REGISTER.CONFIG_STATUS.BIT08_MODE_PIN_M[0] 1
REGISTER.CONFIG_STATUS.BIT09_MODE_PIN_M[1] 0
REGISTER.CONFIG_STATUS.BIT10_MODE_PIN_M[2] 1
REGISTER.CONFIG_STATUS.BIT11_INIT_B_INTERNAL_SIGNAL_STATUS 1
REGISTER.CONFIG_STATUS.BIT12_INIT_B_PIN 1
REGISTER.CONFIG_STATUS.BIT13_DONE_INTERNAL_SIGNAL_STATUS 0
REGISTER.CONFIG_STATUS.BIT14_DONE_PIN 0
REGISTER.CONFIG_STATUS.BIT15_IDCODE_ERROR 0
REGISTER.CONFIG_STATUS.BIT16_SECURITY_ERROR 0
REGISTER.CONFIG_STATUS.BIT17_SYSTEM_MONITOR_OVER-TEMP_ALARM_STATUS 0
REGISTER.CONFIG_STATUS.BIT18_CFG_STARTUP_STATE_MACHINE_PHASE 000
REGISTER.CONFIG_STATUS.BIT21_RESERVED 0000
REGISTER.CONFIG_STATUS.BIT25_CFG_BUS_WIDTH_DETECTION 00
REGISTER.CONFIG_STATUS.BIT27_HMAC_ERROR 0
REGISTER.CONFIG_STATUS.BIT28_PUDC_B_PIN 0
REGISTER.CONFIG_STATUS.BIT29_BAD_PACKET_ERROR 0
REGISTER.CONFIG_STATUS.BIT30_CFGBVS_PIN 1
REGISTER.CONFIG_STATUS.BIT31_RESERVED 0

 

considering the voltage drop/increase i will check and let you know.

Explorer
Posts: 184
Registered: ‎04-11-2016

Re: Error: [Labtools 27-3165] End of startup status: LOW

[ Edited ]

Hi,
thanks sudden voltage drop was the problem.

Visitor
Posts: 1
Registered: ‎05-10-2017

Re: Error: [Labtools 27-3165] End of startup status: LOW

How did you dump the configuration status registers in Vivado?