12-06-2016 06:25 AM - edited 12-06-2016 07:45 AM
I read already some info about it:
but it not seems to be helpful.
I am trying to load .bit file on a custom FPGA(xc7k325) board but getting error as in attachment.
I did as mentioned in the above link:
"PUDC_B must be tied either directly, or via a ≤ 1 kΩ to VCCO_14 or GND." but it didn't work.
surprising to me when I load just simple program (like led blinking) it works but with my program it shows the error. is there any other reason for this error?
Because i have taken a xilinx reference design which is already working with kc705 evaluation board.
only thing I changed here is I mapped the pins as per custom board. All other things is same as evaluation board.
Is there any additional setting needed in project setting during bitstream generation.
12-06-2016 07:39 AM
It's possible that the project causes the FPGA to draw more power than your board can support, which would then lower Vccint enough to reset the FPGA. I would suggest scoping on Vccint as close as possible to the FPGA to see if there is a dip in voltage when you configure the part.
There are two reasons that the voltage could drop, first that it exceeds the capacity of the supply, and second that the sudden increase in current causes the supply to dip briefly and there is not enough bulk bypass capacitance to hold the voltage above the minimum required to retain configuration.
12-06-2016 07:46 AM
here is further info, if it helps to understand the problem:
Status of configuration register:
considering the voltage drop/increase i will check and let you know.