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21,874 Views
Registered: ‎07-20-2013

Error in output declaration

Hi., 

        I wrote a program to read the memory from single port ram as

  

module txete(clka,wea,addra,dina,douta );
input clka;
input wea;
input [13:0]addra;
input [7:0] dina;
output [7:0]douta;

ramq r1(clka,wea,addra,dina,douta);
reg [7:0] rom1 [16383:0];
reg [13:0]addra_reg;
initial
$readmemh("inputHexp.txt", rom1, 0,16383);
always @ (posedge clka)
begin
// Write
if (wea)

addra_reg <= addra;

rom1[addra_reg] <= dina;

assign douta = rom1[addra_reg];

end
endmodule

 

 

but it shows error as: 


ERROR:HDLCompilers:247 - "txete.v" line 22 Reference to vector wire 'douta' is not a legal reg or variable lvalue
ERROR:HDLCompilers:42 - "txete.v" line 22 Illegal left hand side of procedural assign

 

help me to clear this error... 

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6 Replies
vuppala
Xilinx Employee
Xilinx Employee
21,868 Views
Registered: ‎04-16-2012

Hi,

 

These errors occur if signals declared as wire type are assigned a value using an always block statement. 
If a conditional assignment is needed, you must use a reg data type.

Modify your code as below:

 

module txete(clka,wea,addra,dina,douta );

input clka;

input wea;

input [13:0]addra;

input [7:0] dina;

output reg [7:0]douta;

ramq r1(clka,wea,addra,dina,douta);

reg [7:0] rom1 [16383:0];

reg [13:0]addra_reg;

initial

$readmemh("inputHexp.txt", rom1, 0,16383);

always @ (posedge clka)

begin // Write

if (wea)

addra_reg <= addra;

rom1[addra_reg] <= dina;

douta = rom1[addra_reg]; 

end

endmodule

 

Thanks

 

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21,866 Views
Registered: ‎07-20-2013

thanks but it again shows error as: 

 

ERROR:HDLCompilers:246 - "txete.v" line 7 Reference to vector reg 'douta' is not a legal net lvalue
ERROR:HDLCompilers:102 - "txete.v" line 7 Connection to output port 'douta' must be a net lvalue
ERROR:HDLCompilers:246 - "txete.v" line 19 Reference to vector reg 'douta' is not a legal net lvalue
ERROR:HDLCompilers:102 - "txete.v" line 19 Connection to output port 'douta' must be a net lvalue

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vuppala
Xilinx Employee
Xilinx Employee
21,859 Views
Registered: ‎04-16-2012

Hi,

For continuous assignments, you must use wire data type.
So change the code as follows:

module txete(clka,wea,addra,dina,douta );

input clka;
input wea;
input [13:0]addra;
input [7:0] dina;
output [7:0]douta;
reg [7:0] douta1;
ramq r1(clka,wea,addra,dina,douta);
reg [7:0] rom1 [16383:0];
reg [13:0]addra_reg;
initial
$readmemh("inputHexp.txt", rom1, 0,16383);
always @ (posedge clka)
begin // Write
if (wea)
addra_reg <= addra;
rom1[addra_reg] <= dina;
douta1 <= rom1[addra_reg];
end
assign douta = douta1;
endmodule

Thanks
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muzaffer
Teacher
Teacher
21,849 Views
Registered: ‎03-31-2012

you need to move assign douta line out of the always block, put it after "end" and before endmodule. That should fix your problem. But you have another issue: you are connecting douta to both ramq and using it as output of rom1. I am not sure what ramq does but it sure looks like douta is being used as output. This will create a conflict.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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21,772 Views
Registered: ‎10-09-2013

 

hi

im trying to put something on LCD using verilog. 1234.... for now

 

im using the clock and then instenciating a divider module to slow it down 

 

but im also getting the same error as above has been stated...

 

this is my main program:

 

module display_numbers_timer_divide(SW_0,clk, sf_ce0, lcd_rs, lcd_rw, lcd_e, lcd_4, lcd_5, lcd_6, lcd_7);

                             parameter k=18;
(* LOC="L13"*) input SW_0;
(* LOC="C9" *) input clk; // synthesis attribute PERIOD clk "50 MHz"
                             reg [7:0]count=0;
(* LOC="D16" *) output reg sf_ce0; // high for full LCD access
                             reg lcd_busy=1;
                               reg lcd_stb;
                              reg [5:0]lcd_code;
                              reg [6:0]lcd_stuff
                             reg clk_1;
                            reg clk_2;
                               reg clk_3;
(* LOC="L18" *) output reg lcd_rs;
(* LOC="L17" *) output reg lcd_rw;
(* LOC="M15" *) output reg lcd_7;
(* LOC="P17" *) output reg lcd_6;
(* LOC="R16" *) output reg lcd_5;
(* LOC="R15" *) output reg lcd_4;
(* LOC="M18" *) output reg lcd_e;


divider d1 (clk,clk_1);
divider d2 (clk_1,clk_2);
divider d3 (clk_2,clk_3);

always @ (posedge clk_3 )
begin
count <= count + 1;
end

always @ (posedge clk)
begin

sf_ce0 <= 1;

case(count[7:2])
0:lcd_code <= 6'h03; // power-on initialization
1:lcd_code <= 6'h03;
2:lcd_code <= 6'h03;
3:lcd_code <= 6'h02;
4:lcd_code <= 6'h02; // function set
5:lcd_code <= 6'h08;
6:lcd_code <= 6'h00; // entry mode set
7:lcd_code <= 6'h06;
8:lcd_code <= 6'h00; // display on/off control
9:lcd_code <= 6'h0C;
10:lcd_code <= 6'h00; // display clear
11:lcd_code <= 6'h01;
12: lcd_code <= 6'h23; //1
13: lcd_code <= 6'h21;
14: lcd_code <= 6'h23; //2
15: lcd_code <= 6'h22;
16: lcd_code <= 6'h23; //3
17: lcd_code <= 6'h23;
18: lcd_code <= 6'h23; //4
19: lcd_code <= 6'h24;
20: lcd_code <= 6'h23; //5
21: lcd_code <= 6'h25;
22: lcd_code <= 6'h23; //6
23: lcd_code <= 6'h26;
24: lcd_code <= 6'h23; //7
25: lcd_code <= 6'h27;
26: lcd_code <= 6'h23; //8
27: lcd_code <= 6'h28;
28: lcd_code <= 6'h23; //9
30: lcd_code <= 6'h29;

endcase



// if(i<82000) //adding delay
// i<=i+1;

if (lcd_rw) // comment-out for repeating display
lcd_busy <= 0; // comment-out for repeating display

lcd_stb <= ^count[1:0] & ~lcd_rw & lcd_busy; // clkrate / 2^(k+2)
lcd_stuff <= {lcd_stb,lcd_code};
{lcd_e,lcd_rs,lcd_rw,lcd_7,lcd_6,lcd_5,lcd_4} <= lcd_stuff;
end


endmodule

 

 

 

 

and this is my divider program:

 

module divider(Clk_in, Clk_out);

// input ports
input Clk_in;

// output ports
output reg Clk_out = 1'b0; // provide initial condition for this register.

// counter size calculation according to input and output frequencies
parameter sys_clk = 50000000; // 50 MHz system clock
parameter clk_out = 1000000; // 1 MHz clock output
parameter max = sys_clk / (2*clk_out); // max-counter size

reg [4:0]counter = 0; // 5-bit counter size

always@(posedge Clk_in) begin
if (counter == max-1)
begin
counter <= 0;
Clk_out <= ~Clk_out;
end
else
begin
counter <= counter + 1'd1;
end
end
endmodule

 

 

the error that i get when i simulate my main program is:

 

ERROR:HDLCompilers:246 - "display_numbers_timer_divide.v" line 45 Reference to scalar reg 'clk_1' is not a legal net lvalue
ERROR:HDLCompilers:102 - "display_numbers_timer_divide.v" line 45 Connection to output port 'Clk_out' must be a net lvalue
ERROR:HDLCompilers:246 - "display_numbers_timer_divide.v" line 46 Reference to scalar reg 'clk_2' is not a legal net lvalue
ERROR:HDLCompilers:102 - "display_numbers_timer_divide.v" line 46 Connection to output port 'Clk_out' must be a net lvalue
ERROR:HDLCompilers:246 - "display_numbers_timer_divide.v" line 47 Reference to scalar reg 'clk_3' is not a legal net lvalue
ERROR:HDLCompilers:102 - "display_numbers_timer_divide.v" line 47 Connection to output port 'Clk_out' must be a net lvalue

 

 

 

Tags (1)
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muzaffer
Teacher
Teacher
21,769 Views
Registered: ‎03-31-2012

You need to declare clk_1, clk_2 and clk_3 as wire instead of reg. Also in module divider you have a port named Clk_out and a parameter named clk_out. It is very error prone to depend on the case sensitivity of Verilog. I suggest that you rename the clk_out parameter so something like clk_out_scaler.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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