Error while synthetize. Signal can't be synthetized.
I am working in a wishborne bus and I have the next problem when I synthetize:
line 122: Signal data<0> cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
The problem is here:
process (RST_I, DATp_I, DATm_I, cnt2) begin if (rising_edge(RST_I)) then cnt <= 0; data <= (others => '0'); elsif (rising_edge(DATp_I) and cnt <4) then data(cnt) <= DATp_I; cnt<= cnt+1; elsif (rising_edge(DATm_I) and cnt <4)then cnt<= cnt+1; data(cnt) <= DATm_I; elsif (cnt2 = count_module) then cnt <= 0; data <= (others => '0'); end if; end process;
You should listen to what the tool is telling you: the code you have is not proper synchronous description and can not be synthesized as written. You need to read about synthesizable VHDL and change your code accordingly.
Here is a clue: wishbone spec says: "The clock input [CLK_I] coordinates all activities for the internal logic within the WISHBONE interconnect. All WISHBONE output signals are registered at the rising edge of [CLK_I]. All WISHBONE input signals are stable before the rising edge of [CLK_I]."
This means you can depend on only rising edge of CLK_I and all other signals can be checked on this edge and no other edge signals are necessary.
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