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Observer
Observer
2,503 Views
Registered: ‎11-14-2016

FIFO generator IP

I am using Common clock builtin FIFO IP (FIFO Generator v13.1). However I don't see any option to select the desired clock frequency. I see the option when it is independent clock FIFO. When common clock FIFO synthesis is run, it is giving the below warning:

 

[Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'fifo' at clock pin 'clk' is different from the actual clock period '5.000', this can result in different synthesis results.

 

Please note that 5.000 is being extracted from the 5ns constraint for clk that I specified. No clue where it is taking 10.000 from.

Subsequently the timing is not met

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2 Replies
Explorer
Explorer
2,472 Views
Registered: ‎04-12-2017

When the FIFO is synthesized OOC the block still doesn't "know" that you have a constraint for it in the instantiating block. However, once all the design is synthesized the FIFO does know now what is the constraint. If you have a timing problem it is not related to the warning you receive during FIFO OOC synthesis.

Avi Chami MSc
FPGA Site
Observer
Observer
2,354 Views
Registered: ‎11-14-2016

@a_chami

Any idea what the warning is about and where the tool is taking 10ns from?

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