05-15-2017 03:30 AM
I am using Windows 7. Firmware platform is Vivado Version 2015.2 and simulator is ISIM.
I am having issues with FIFO. FIFO is not reading the data . FIFO is a sub part of my design in which I am storing the data coming from FFT into it. The data placed in FIFO is to be read by another module for further processing. I am getting all the FIFO flags correctly as can be seen in the attachment but somehow FIFO's output is having ambiguous values (indicated by red signal) in attachment. Kindly tell me how to sort this out.
05-15-2017 05:01 AM - edited 05-15-2017 05:08 AM
are you resetting your fifo before usage? Fifo's require a reset pulse of minimum 5 WRCLK cycles (in case of dual domain fifo's, you need to take the slowest clock).
from UG473 - FIFO PORTS : WREN
Write enable. When WREN = 1, data is written to memory. When WREN = 0, write is disabled. WREN and RDEN must be held Low before and during the Reset cycle. In addition, WREN and RDEN should be held Low for two WRCLK and RDCLK cycles, respectively, after the Reset is deasserted to guarantee timing.