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Observer sarmad_wahab
Observer
2,112 Views
Registered: ‎11-07-2016

FPGA 7 Series Artix VHDL Code Implementation Problem

Hi,

        I have designed wrapper for wishbone slave interface and MIG DDR3 SDRAM User interface for FPGA 7 series Artix. In simulations (Test Bench) it is working fine wishbone send's ten different data's for writing and read's the same ten data accurately everything is perfect and smooth. Moreover my wrapper is synthesized it has no critical warnings or errors. I have created top module which consists of my wrapper and MIG user interface. When ever I synthesize top module the ok status is ticked but has some critical warnings from MIG. whenever I implement my code on FPGA , It doesn't work. My supervisor confirmed that he has used other wrapper with same MIG and it is working fine. What can be the possible reason, does reset (asynchronous/synchronous) has effect on hardware implementation. Below I have attached my code along with images regarding errors,schematic and status of my top module.

 

Best Regards,
Sarmad Wahab

Top_Module_Synthesize_Status.png
Critical_Errors_Warnings.png
RTL_SCHEMATIC_TOP_MODULE.png
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2 Replies
Teacher muzaffer
Teacher
2,095 Views
Registered: ‎03-31-2012

Re: FPGA 7 Series Artix VHDL Code Implementation Problem

@sarmad_wahab It seems like you have all that you need to fix your problem. You need to go through the critical warnings and clean them up. Then run your simulations again but use the timing annotated implementation level netlist for your own IP instead of the RTL version and debug to see why it doesn't work (so testbench and MIG stay the same but the wrapper uses the implementation netlist). Just dumping your code here is probably not going to be very productive.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Observer sarmad_wahab
Observer
2,087 Views
Registered: ‎11-07-2016

Re: FPGA 7 Series Artix VHDL Code Implementation Problem

@muzaffer Thanks for reply, my wrapper is free from critical warnings these warnings are from MIG by CoreGen. I am not that much advanced can you please tell how to perform exactly timing annotated implementation level netlist. I am using vivado
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