12-16-2016 04:55 AM
I am using ultrascale FPGA board. I am able to transfer data from PC to DDR on board through DMA subsystem IP and DDR controller IP. I am planning to do some processing in FPGA and then update the data so that it can be read by PC. How do I indicate PC that the processing is over through PCIe?
Is there any example design which can generate an interrupt on PC from FPGA through PCIe DMA subsystem. Also how to write the interrupt service routine on PC side which gets triggered by PCIe interrupt?
12-16-2016 07:10 AM
@nikhilmahesh Yes, you can send MSI (message signaled interrupt) to the PC over the link. You need to configure your end-point to request interrupts during enumeration which tells to PC to allocate interrupts on its side. Then you can just trigger MSI on the FPGA with very simple logic. It is simply the value of the interrupt you need to trigger and a start signal and a return which says that it has been acknowledged. Look at Xilinx PCIe end-point documentation. On the PC side, it's standard interrupt handling code which changes per your OS.
12-17-2016 09:54 AM
Please let me know if my understanding below is correct.
Generating interrupt from FPGA side
usr_irq_req of DMA subsystem IP has to be made high and we need to wait until usr_irq_ack goes high. This will send an interrupt to PC through PCIe. Also we need to wait for another usr_irq_ack before triggering another interrupt.
Handling interrupt in PC side
I am not really clear on how to do this side. Can someone point me to a hello world program for PCIe interrupt or other documentation. I am doing this in Ubuntu 16.04. When I search for materials in web, the results show complicated details of linux.
12-17-2016 10:08 AM
@nikhilmahesh not sure about usr_irq_req. In the axi memory mapped to pcie ip I used, I am pretty sure the msi request had some mention of msi in its name. Maybe your block doesn't but I'd read the docs again to make sure usr_irq_req is the right one.
As to linux pcie interrupt handling you can start here: http://stackoverflow.com/questions/24264030/pcie-interrupt-number
There is a how which shows how to write a linux kernel driver to manage the pcie enumeration, msi enabling etc. Also check this out: http://haifux.org/lectures/256/haifux-pcie.pdf