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Visitor rapatil_rtg
Visitor
7,549 Views
Registered: ‎07-18-2013

Floating point number synthesis

How to synthesize floating point number in xilinx?

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9 Replies
Scholar austin
Scholar
7,545 Views
Registered: ‎02-27-2008

Re: Floating point number synthesis

Why?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Xilinx Employee
Xilinx Employee
7,516 Views
Registered: ‎11-28-2007

Re: Floating point number synthesis

Please take a look at Vivado High Level Synthesis (VHLS). You can use C/C++ for your floating point operations and the tool will instantiate floating point cores during C-synthesis.

 

http://www.xilinx.com/products/design-tools/vivado/integration/esl-design/index.htm

Cheers,
Jim
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Historian
Historian
7,506 Views
Registered: ‎02-25-2008

Re: Floating point number synthesis


@ywu wrote:

Please take a look at Vivado High Level Synthesis (VHLS). You can use C/C++ for your floating point operations and the tool will instantiate floating point cores during C-synthesis.

 

http://www.xilinx.com/products/design-tools/vivado/integration/esl-design/index.htm


He's gonna need a bigger chip.

----------------------------Yes, I do this for a living.
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Visitor lamiastella
Visitor
7,482 Views
Registered: ‎11-28-2012

Re: Floating point number synthesis

Hi,

So you don't suggest using ISE for operation on 1D and 2D arrays of floating point numbers? Does the C code get converted to HDL level? As I want something that runs my C code much faster than my own computer CPU and don't like to run the C code in Kintex7 MicroBlaze or soft cores.
If there are any link regarding how to do operations on floating point array of numbers in Vivado or ISE, that'll be great if you can share it.

 

Best regards,

Mona Jalal.

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Scholar markcurry
Scholar
7,469 Views
Registered: ‎09-16-2009

Re: Floating point number synthesis

 

You're not going to find many pointers to existing documents and solutions - floating point's just not very common in FPGA designs.  There's many reasons for this - some hinted here (you'll need a big FPGA).  Other forum posts talk about this more.

 

There's rare exceptions where some sort of "floating point" may be needed in an FPGA - but it's just that - an exception. And even those solutions are not going to implement full "floating point" math.  Most FPGA designs use some sort of fixed point. 

 

For those that don't wish to learn fixed point - Xilinx provides some of those floating point cores, and other Sysgen solutions.  I've never used them, so can't really comment much on them.  But Bassman's comments are valid - "You're going to need a bigger chip".  Floating point solutions are inefficient on FPGAs.

 

Regards,

 

Mark

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Scholar austin
Scholar
7,466 Views
Registered: ‎02-27-2008

Re: Floating point number synthesis

Mark,

 

Agreed.  But -- if you design a fixed point solution with the proper range and domain, you can them duplicate enough logic (in parallel) so you may be able to solve a row, a column, or at least a small block of data on a single clock cycle, making the FPGA solution 20 to 100 times faster than a GPU solution, and 20 to 100 times less power.

 

If it MUST be floating point, then you may still get a 4 to 8x speedup (over a CPU, but a GPU will be faster, but much more power, too), but you will need a BIG device, and implementing FPU's in FPGA requires tons of resources.  The good news is that if you can trim the FPU to be ONLY a FPU multiplier, and ONLY a FPU adder, then the logic resources are minimized.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Scholar markcurry
Scholar
7,462 Views
Registered: ‎09-16-2009

Re: Floating point number synthesis

Austin,

 

We're in agreement here.  And let me explain my last line:

 

"Floating point solutions are inefficient on FPGAs."

 

That wasn't a condemnation on Xilinx (or any other FPGA family) for somehow dropping the ball. It's the nature of the beast.  An FPGA is being used to solve a specific problem.  General "Floating point" solutions are needed for general processors, where the problems just aren't bound.

 

There's no need for a number format on a specific wire inside a FPGA to be able to represent both the distance between atoms, and the distance between stars.  (I'm exaggerating here - I don't think the dynamic range's that large).  Instead the designer implements a solution that meets the specific needs of the problem at hand.

 

Regards,

 

Mark

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Scholar austin
Scholar
7,459 Views
Registered: ‎02-27-2008

Re: Floating point number synthesis

Mark,

 

Yes.  We are in 'violent agreement.'  I know you were not 'blaming' the FPGA, I was reinforcing what had said, from the Xilinx perspective.

 

Than you for your clear and concise explanations on this subject.

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor rapatil_rtg
Visitor
7,335 Views
Registered: ‎07-18-2013

Error in synthesis

I am getting error during synthesis of following program written in VHDL.

See the attachment

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