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3,139 Views
Registered: ‎12-03-2014

GTP Transceiver Spartan 6

Hi all,

 

How to send some data on GTP, if you have any example files please share with me, i want to send only data i don't require any chipscope, i tried but i am encountering with an error.

Regards,

Pavan Patil
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Xilinx Employee
Xilinx Employee
3,137 Views
Registered: ‎02-06-2013

Hi

 

You can use the example design generated with the core.

 

Refer PG168 for more details.

Regards,

Satish

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Xilinx Employee
Xilinx Employee
3,136 Views
Registered: ‎07-11-2011

HI,

 

You can use quick start example design,  below link gives you steps to create the core, simulate and implement it

http://www.xilinx.com/support/documentation/ip_documentation/s6_gtpwizard_gsg546.pdf

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3,103 Views
Registered: ‎12-03-2014

Hi,

i have gone through that document, i need some timing diagrams related to that design if you have please add it here.

thank you

Regards,

Pavan Patil
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3,096 Views
Registered: ‎12-03-2014

how to analyse the sollution from simulation

Regards,

Pavan Patil
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Xilinx Employee
Xilinx Employee
3,095 Views
Registered: ‎02-06-2013

Hi

 

 

We don't have any separte timing diagrams.

 

Simulate the example desgin and observe the data interfaces.

Regards,

Satish

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Registered: ‎12-03-2014

Hi

Suppose if i am having RX_IN[1:0] as an input to my GTP and Reference_clk of both N and P(GTP_REFCLK_P,GTP_REFCLK_N). now what is my TX_OUT will be based on the GTP.

and up to how much clk we can give .

Regards,

Pavan Patil
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Xilinx Employee
Xilinx Employee
3,049 Views
Registered: ‎02-06-2013

Hi

 

 

The Rxp and Rxn serial data will be decoded and gives you paralled data on rxdata and similarly the paralled data will be encoded, serilized and send on txp and txn.

 

The clock frequency depends on the protocol and the frequency you have selected in the gt wizard while customisation.

 

Refer below doc for detailed description of the transmitter and receiver of the transceiver and about the clocing.

 

http://www.xilinx.com/support/documentation/user_guides/ug386.pdf

 

In the example design the frame gen module provides data on the txdata and the serial data is looped and the parallel rx data is checked in the frame checker.

Regards,

Satish

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