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Visitor checkandmate
Visitor
3,065 Views
Registered: ‎05-02-2017

Generate eye diagram using IBERT without loopback

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Hi,

I have an AD9625 ADC (Datasheet) being routed to 8 GTX ports on an xc7z045ffg676-2. I want to view the eye diagram using IBERT 3.0. All examples and documents I can find use a loopback to test the GTX ports (i.e. one GTX port is the TX and another is the RX).

 

The following is the instantiation of the IBERT block in the top module.

 

    ibert_7series_gtx_0 ibert_0 //Generating iBert block in top level
    (
      .TXN_O          (),
      .TXP_O          (),
      .RXOUTCLK_O     (),
      .RXN_I          (SERDOUT_n), //8-bit JESD204b N
      .RXP_I          (SERDOUT_p), //8-bit JESD204b P
      .GTREFCLK0_I    (divclk_2bit), //625Mhz clock
      .GTREFCLK1_I    (),
      .SYSCLK_I       (rxclk) //156.25MHz clock
    );

 

My iBERT IP is as follows:

 

ibert1.PNG

ibert2.PNG 

I am able to generate a bitstream file and program the FPGA but I cannot produce a 2D eye diagram as I have no links due to my external TX source.

 

Is it possible to get an eye diagram using IBERT 3.0 without using the loopback feature?

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1 Solution

Accepted Solutions
Visitor checkandmate
Visitor
5,007 Views
Registered: ‎05-02-2017

Re: Generate eye diagram using IBERT without loopback

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I have solved this issue a while ago now but forgot to update this forum. I used this diagram from ug476:

Capture.PNG

It turns out my QPLL divider, N, was set to 20. However, with a refclk of 625MHz and a line rate of 6.25Gbps, I needed it to be 10. Having N=10 was not an option so I set my refclk to half of its previous value by using the div2 output in the IBUFDS_GTE2 block that my external clock was coming into:

 

  IBUFDS_GTE2 #(
    .CLKCM_CFG("TRUE"), // Refer to Transceiver User Guide
    .CLKRCV_TRST("TRUE"), // Refer to Transceiver User Guide
    .CLKSWING_CFG(2'b11) // Refer to Transceiver User Guide
  )
    IBUFDS_GTE2_inst (
    .O    (), // 1-bit output: Refer to Transceiver User Guide
    .ODIV2(divclk_div2), // 1-bit output: Refer to Transceiver User Guide
    .CEB  (1'b0), // 1-bit input: Refer to Transceiver User Guide
    .I    (divclk_p), // 1-bit input: Refer to Transceiver User Guide
    .IB   (divclk_n) // 1-bit input: Refer to Transceiver User Guide
  );

Another easier option would have been to simply set M=2 in the hardware manager.

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5 Replies
Advisor evgenis1
Advisor
3,040 Views
Registered: ‎12-03-2007

Re: Generate eye diagram using IBERT without loopback

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Hi,

 

You can turn off loopback in Vivado IBERT GUI, by selecting Loopback=None. See attached screenshot.

 

Thanks,

Evgeni

Tags (1)
ibert1.jpg
Visitor checkandmate
Visitor
2,980 Views
Registered: ‎05-02-2017

Re: Generate eye diagram using IBERT without loopback

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Hi Evgeni,

 

Thanks for the response! I do have it set to none. Unfortunately I still get no links. I am using Vivado 2015.4. Another issue might be related to my system clock, rxclk, which is an internal clock while in the clock settings tab there is no other option than external:

 

ibert3.PNG

Pin G7 is simply an unused pin.

 

My external clock sources are very limited so I wanted to use the internal clock instead. Looking at the implemented design, the rxclk net is the same as the SYSCLK_I net so it seems as though the internal clock is the one being connected. Is there a way to set an internal option in the IP block?

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Explorer
Explorer
2,967 Views
Registered: ‎10-14-2015

Re: Generate eye diagram using IBERT without loopback

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Hi @checkandmate

 

Please change the Near end PMA and PCS loopback option In GUI to see the you see the Link .

 

Thanks,

Sarada

 

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Visitor checkandmate
Visitor
2,910 Views
Registered: ‎05-02-2017

Re: Generate eye diagram using IBERT without loopback

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Hi @saradapr 

 

I have tried all types of loopbacks with no luck. I have also tried outputting a variety of patterns from the ADC, again with no success.

 

Thanks,

Mate

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Visitor checkandmate
Visitor
5,008 Views
Registered: ‎05-02-2017

Re: Generate eye diagram using IBERT without loopback

Jump to solution

I have solved this issue a while ago now but forgot to update this forum. I used this diagram from ug476:

Capture.PNG

It turns out my QPLL divider, N, was set to 20. However, with a refclk of 625MHz and a line rate of 6.25Gbps, I needed it to be 10. Having N=10 was not an option so I set my refclk to half of its previous value by using the div2 output in the IBUFDS_GTE2 block that my external clock was coming into:

 

  IBUFDS_GTE2 #(
    .CLKCM_CFG("TRUE"), // Refer to Transceiver User Guide
    .CLKRCV_TRST("TRUE"), // Refer to Transceiver User Guide
    .CLKSWING_CFG(2'b11) // Refer to Transceiver User Guide
  )
    IBUFDS_GTE2_inst (
    .O    (), // 1-bit output: Refer to Transceiver User Guide
    .ODIV2(divclk_div2), // 1-bit output: Refer to Transceiver User Guide
    .CEB  (1'b0), // 1-bit input: Refer to Transceiver User Guide
    .I    (divclk_p), // 1-bit input: Refer to Transceiver User Guide
    .IB   (divclk_n) // 1-bit input: Refer to Transceiver User Guide
  );

Another easier option would have been to simply set M=2 in the hardware manager.

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