09-19-2016 10:53 PM
I am using a Kintex - 7 series FPGA, in which my current design has a ten-gig-eth PCS block along with GTX transceiver from Coregen.
I want to put the PCS block inside the GTX i.e., the GTX should take care of the PCS functionality so that I can free some LUTs (currently used by PCS) for other logic. How can I do that ?
09-19-2016 11:54 PM
If I understood it correctly, you are trying to put shared logic in core instead of example design (where it gets implemented in FPGA fabric). If this is correct, then you have option of selecting this while customizing GT wizard.
Please check attached snapshot.
09-20-2016 12:04 AM
No, actually this will only encrypt the shared logic and put it inside the core. This won't effect the LUT utilization. I want to reduce the LUT utilization currently taken up by the PCS logic.
At present, PCS block is instantiated inside the GTX as a separate module. I want the functionality of PCS logic to be taken care by the GTX itself. So that I can get some free area in the FPGA.
09-20-2016 12:16 AM
At present, PCS block is instantiated inside the GTX as a separate module
--> Can you please let us know name of this module which you are referring to?
09-20-2016 12:20 AM
09-20-2016 12:26 AM
The pcs logic is part of the ngc file delivered with the core in ISE and there is no way you can separate the PCS logic from the core and implement this in the Transceiver.