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Participant gtushar
Participant
3,910 Views
Registered: ‎02-08-2016

How do I enable the PCS functionality of GTX - 7 series FPGA

I am using a Kintex - 7 series FPGA, in which my current design has a ten-gig-eth PCS block along with GTX transceiver from Coregen.

I want to put the PCS block inside the GTX i.e., the GTX should take care of the PCS functionality so that I can free some LUTs (currently used by PCS) for other logic. How can I do that ?

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5 Replies
Xilinx Employee
Xilinx Employee
3,895 Views
Registered: ‎02-14-2014

Re: How do I enable the PCS functionality of GTX - 7 series FPGA

Hello @gtushar,

 

If I understood it correctly, you are trying to put shared logic in core instead of example design (where it gets implemented in FPGA fabric). If this is correct, then you have option of selecting this while customizing GT wizard. 

Please check attached snapshot.

Regards,
Ashish
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Participant gtushar
Participant
3,887 Views
Registered: ‎02-08-2016

Re: How do I enable the PCS functionality of GTX - 7 series FPGA

Hi @ashishd

 

No, actually this will only encrypt the shared logic and put it inside the core. This won't effect the LUT utilization. I want to reduce the LUT utilization currently taken up by the PCS logic.

At present, PCS block is instantiated inside the GTX as a separate module. I want the functionality of PCS logic to be taken care by the GTX itself. So that I can get some free area in the FPGA.

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Xilinx Employee
Xilinx Employee
3,882 Views
Registered: ‎02-14-2014

Re: How do I enable the PCS functionality of GTX - 7 series FPGA

Hello @gtushar,

 

At present, PCS block is instantiated inside the GTX as a separate module

 

--> Can you please let us know name of this module which you are referring to?

Regards,
Ashish
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Participant gtushar
Participant
3,880 Views
Registered: ‎02-08-2016

Re: How do I enable the PCS functionality of GTX - 7 series FPGA

Hi @ashishd

 

Actually I am using Xilinx 14.7 right now. And it generates the file name as ten_gig_eth_pcs.vhd instantiated under ten_gig_eth_pcs_block.vhd

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Xilinx Employee
Xilinx Employee
3,876 Views
Registered: ‎02-06-2013

Re: How do I enable the PCS functionality of GTX - 7 series FPGA

Hi

 

The pcs logic is part of the ngc file delivered with the core in ISE and there is no way you can separate the PCS logic from the core and implement this in the Transceiver.

Regards,

Satish

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