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Visitor
Visitor
7,587 Views
Registered: ‎02-16-2016

How does Timing Constraints editor recognize clocks in a design?

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Hi there,

 

For example in a code, some inputs are mentioned as clock signals and we can apply period constraints on them. But apart from them, sometimes the constraint editor also shows some other signals in the list of unconstrained clocks.

 

So, my doubt is how does the Timing Constraints editor recognize clocks in a design?

Is it enough if period constraint is applied only on those signals listed as unconstrained clocks in the editor?

How to be sure if one has covered all the paths between synchronous elements in a design?

 

 Thanks.

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Xilinx Employee
Xilinx Employee
14,663 Views
Registered: ‎10-24-2013

Hi @such_06

The constraints editor will treat all the signals driving the sequential elements' clock input as clocks. Please check the technology schematic (post-synthesis view of the design) and look for the signals of interest. Make sure that they don't drive any clock input ports/pins. I strongly believe they would be driving the clock pins.

You should also check for unintended latches. You should get warnings if a latch is inferred. The Gate input of a transparent latch is considered a "clock" by the tools.

Thanks,Vijay
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Xilinx Employee
Xilinx Employee
14,664 Views
Registered: ‎10-24-2013

Hi @such_06

The constraints editor will treat all the signals driving the sequential elements' clock input as clocks. Please check the technology schematic (post-synthesis view of the design) and look for the signals of interest. Make sure that they don't drive any clock input ports/pins. I strongly believe they would be driving the clock pins.

You should also check for unintended latches. You should get warnings if a latch is inferred. The Gate input of a transparent latch is considered a "clock" by the tools.

Thanks,Vijay
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Xilinx Employee
Xilinx Employee
7,535 Views
Registered: ‎10-24-2013

Hi @such_06

 

Did my last post answered your query?

Thanks,Vijay
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Visitor
Visitor
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Registered: ‎02-16-2016

I checked the technology schematic and found that the signals drive clock pin of flip flops. The signals are derived from one of the main clocks.

This is a cpld(xc95288xl) based design. I related the two clocks as shown in the screenshot and in the timing report I saw that the constraint was met. I tried to use below syntax to relate them.

 

NET "Timing/Q_counter_s<2>" TNM_NET = Timing/Q_counter_s<2>;
TIMESPEC TS_Timing_Q_counter_s_2 = PERIOD "Timing/Q_counter_s<2>" TS_CLK_20kHz_ip/2 HIGH 50%;

 

But I got an error as shown in the screenshot. So, I wanted to know what is the correct way to relate clocks in this case?

 

Thanks.

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Xilinx Employee
Xilinx Employee
7,478 Views
Registered: ‎10-24-2013

Hi @such_06

 

Good to see that your query is answered.Close the thread by marking the solution in the interest of other users.

Can you please create a new thread for the follow-up query?

Thanks,Vijay
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Visitor
Visitor
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Registered: ‎02-16-2016

Sure. I will post a separate query for that. Thanks.

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