UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor qscgy246
Visitor
7,833 Views
Registered: ‎02-03-2016

How to add Source file

Hi!

I tried to Creating  Custom AXI Slave Interfaces Part2 (Lesson6) video.

I want to add a CountNumberOfPattern file to the myip_v1_0_S01_AXI_inst file like under the attachments.

How can i add the file?

error8.png
error7.png
0 Kudos
5 Replies
Moderator
Moderator
7,829 Views
Registered: ‎07-01-2015

Re: How to add Source file

Hi @qscgy246,

 

Do you mean you want to add .v or .vhd file to a custom IP?

Add the file in source window. If the file is reflected in hierarchy then it should get reflected while packaging the IP.

 

If you already have the custom IP then open it in IP packager then add the required files.

Save changes and repackage the IP.

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
1.JPG
2.jpg
0 Kudos
Moderator
Moderator
7,817 Views
Registered: ‎01-16-2013

Re: How to add Source file

@qscgy246,

 

In the IP Packager under File groups, Right click on the File group (VHDL Synthesis) and select Add FIles.

 

Capture.PNG

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
Visitor qscgy246
Visitor
7,808 Views
Registered: ‎02-03-2016

Re: How to add Source file

i want to add .sv file

add files click then doesn't exist .sv file

0 Kudos
Explorer
Explorer
7,803 Views
Registered: ‎10-14-2015

Re: How to add Source file

Hi @qscgy246,

 

Please see the discussion below link:

 

https://forums.xilinx.com/t5/Design-Entry/Interesting-System-Verilog-files-with-v-extension/td-p/401311

 

Thanks,

Sarada

 

--------------------------------------------------​​--------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.

--------------------------------------------------​​--------------------------------------------

0 Kudos
Visitor qscgy246
Visitor
7,788 Views
Registered: ‎02-03-2016

Re: How to add Source file

that is not my concern

i want to .sv file conbine .v file

please open the my attachment image

0 Kudos