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Registered: ‎04-18-2017

How to disable HDL code optimization in Vivado

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Hello all,
When I tried to synthesis an HDL code using Vivado to create an LUT in which the LSB defines the logic state (i.e 0 or 1) and the remaining bits define the path, after synthesis tool optimized my code and output became the function of LSB only, But I want to include the remaining bits in output function. I also tried using DONT_TOUCH attribute still the logic is optimized.  Is there any way to do this?

Thank you.

Here is my VHDL code :

architecture Behavioral of LUT is
begin

First_LUT : process (Inp)
    begin
        case Inp is
            when "0000" => out1 <= '1';
            when "0001" => out1 <= '0';
            when "0010" => out1 <= '1';
            when "0011" => out1 <= '0';

            when "0100" => out1 <= '1';
            when "0101" => out1 <= '0';
            when "0110" => out1 <= '1';
            when "0111" => out1 <= '0';
            
            when "1000" => out1 <= '1';
            when "1001" => out1 <= '0';
            when "1010" => out1 <= '1';
            when "1011" => out1 <= '0';            
            
            when "1100" => out1 <= '1';
            when "1101" => out1 <= '0';
            when "1110" => out1 <= '1';
            when "1111" => out1 <= '0';
       end case;
end process;
end Behavioral;

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Teacher
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Registered: ‎03-31-2012

Re: How to disable HDL code optimization in Vivado

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@sajidkhan2912 you can make such a function using a single lookup table in the FPGA. Your best bet is to implement each mux you see in the diagram individually and map them to separate lookup tables. At that level you can keep each instance and even though wasteful get each of them implemented independently. With the placement and routing differences, you would get the circuit you want.

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Teacher
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Registered: ‎03-31-2012

Re: How to disable HDL code optimization in Vivado

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@sajidkhan2912 your LUT entity has just one bit output which is the inverse of the inp input. There is nothing to not optimize or keep here. Describe the actual intent of your output using some other means so that a meaningful response can be generated for your question.

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Registered: ‎04-18-2017

Re: How to disable HDL code optimization in Vivado

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Dear Sir,

 I want the other inputs as a path selector to create some path delay so that different delay can be achieved using different input values.

Than you for your response.

 

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Registered: ‎03-31-2012

Re: How to disable HDL code optimization in Vivado

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@sajidkhan2912 

 

>>  I want the other inputs as a path selector to create some path delay so that different delay can be achieved using different input values.

 

for digital logic that statement makes no sense. Show the functionality you want through some other language/representation/block diagram etc. so that a meaningful response can be formed.

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Teacher
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Registered: ‎11-14-2011

Re: How to disable HDL code optimization in Vivado

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To achieve your ultimate aim, it would be better to tell us (as precisely as you can) what it is you want to do.

 

At least one of the points of synthesis is to simplify the input HDL to most efficient logic possible. This is subsequently easier for the map and PAR tools to do their job and leaves more FPGA for you to use for other functions.

 

Delay is an interesting concept in the world of FPGA, being inherently synchronous devices, and (by the sounds of it) you are trying to use the device routing to produce some sort of configurable delay. If this is what you want, this will not end well.

 

You would be better using a sufficiently high frequency clock to create a counter and tap off the counter for your desired *synchronous* delay.

 

Or just tell us what you want to do and we'll try to help ... 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Registered: ‎04-18-2017

Re: How to disable HDL code optimization in Vivado

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I am trying to implement a PUF( Physically Unclonable Function) using LUTs, In which the LSB acts a NOT gate and remaining bits gives freedom to select different paths for different delays as there are some process variation during fabrication which makes the path non identical. Please refer the attached image.

0htLQ.png
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Teacher
Teacher
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Registered: ‎11-14-2011

Re: How to disable HDL code optimization in Vivado

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Have you read this thread on the communities -> Manual Route to explore delay PUF ?

 

You could well be in for a long road ahead. This is not my area so I can't really contribute beyond my initial assertion that searching for unpredictable but repeatable delays in the FPGA routing is going to be a headache.

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Teacher
Teacher
8,046 Views
Registered: ‎03-31-2012

Re: How to disable HDL code optimization in Vivado

Jump to solution

@sajidkhan2912 you can make such a function using a single lookup table in the FPGA. Your best bet is to implement each mux you see in the diagram individually and map them to separate lookup tables. At that level you can keep each instance and even though wasteful get each of them implemented independently. With the placement and routing differences, you would get the circuit you want.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post