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naveengk14
Explorer
Explorer
4,381 Views
Registered: ‎09-16-2013

How to fix setup and Hold volation

Hi all,

 

How to fix setup and Hold volation...?

 

 

Thanks
Naveen G K
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6 Replies
arpansur
Moderator
Moderator
4,378 Views
Registered: ‎07-01-2015

Hi @naveengk14,

 

If you want to get more idea on timing closure please go through following links

http://www.xilinx.com/training/fpga/timing-closure-video.htm (ISE)

http://www.xilinx.com/training/vivado/vivado-timing-closure-techniques-physical-optimization.htm (Vivado)

 

Please let us know your exact requirement and the tool you are using to suggest you in better way.

If possible please share the timing report.

 

Thanks,
Arpan

Thanks,
Arpan
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naveengk14
Explorer
Explorer
4,370 Views
Registered: ‎09-16-2013

hi,

 

 

Please find below attachement...

 

Slack (setup path): -1.537ns (requirement - (data path - clock path skew + uncertainty))

   Source:               dec_WRP/header_validin_sig (FF) 
   Destination:          dec_WRP/header_sig1_15 (FF) 
   Requirement:          6.250ns 
   Data Path Delay:      6.994ns (Levels of Logic = 1) 
   Clock Path Skew:      -0.758ns (0.778 - 1.536) 
   Source Clock:         i_deserial_clk_50M rising at 0.000ns 
   Destination Clock:    i_deserial_clk_50M falling at 6.250ns 
   Clock Uncertainty:    0.035ns 
 
   Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
     Total System Jitter (TSJ):  0.070ns 
     Total Input Jitter (TIJ):   0.000ns 
     Discrete Jitter (DJ):       0.000ns 
     Phase Error (PE):           0.000ns 

 

Thanks
Naveen G K
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arpansur
Moderator
Moderator
4,368 Views
Registered: ‎07-01-2015

Hi @naveengk14,

 

Can you please try with smart explorer and let us know if it resolves your issue.

To get more details on smart explorer please go through the following links
http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_using_smart_xplorer.htm

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ug689.pdf

 

Please let us know if you need more clarification on the above details.

 

Thanks,
Arpan

Thanks,
Arpan
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Give Kudos to a post which you think is helpful and reply oriented.
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arpansur
Moderator
Moderator
4,361 Views
Registered: ‎07-01-2015

Hi @naveengk14,

 

From the timing report what I can understand is only set-up violation is there. May be packing the logics tightly from the failing path will help to meet timing.

 

Please go through following link. It gives some recommendations to meet timing closure. Hope this will be helpful to you
http://www.xilinx.com/itp/xilinx10/isehelp/dec_c_timing_closure_recommendations.htm

 

If possible please share your archived design file here.

 

Thanks,
Arpan

Thanks,
Arpan
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naveengk14
Explorer
Explorer
4,331 Views
Registered: ‎09-16-2013

Hi arpansur,

 

Thanks..

 

Problem is solved by using smartxplorer,

Thanks
Naveen G K
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arpansur
Moderator
Moderator
4,329 Views
Registered: ‎07-01-2015

Hi @naveengk14,

 

That's great. Glad to know your issue is resolved.

 

As your issue is resolved please close this thread by marking "Accept as solution" to the answer that led you to solution.

 

Thanks,
Arpan

Thanks,
Arpan
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Give Kudos to a post which you think is helpful and reply oriented.
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