12-12-2015 09:47 PM
If you want to get more idea on timing closure please go through following links
Please let us know your exact requirement and the tool you are using to suggest you in better way.
If possible please share the timing report.
12-12-2015 10:22 PM
Please find below attachement...
Slack (setup path): -1.537ns (requirement - (data path - clock path skew + uncertainty))
Source: dec_WRP/header_validin_sig (FF)
Destination: dec_WRP/header_sig1_15 (FF)
Data Path Delay: 6.994ns (Levels of Logic = 1)
Clock Path Skew: -0.758ns (0.778 - 1.536)
Source Clock: i_deserial_clk_50M rising at 0.000ns
Destination Clock: i_deserial_clk_50M falling at 6.250ns
Clock Uncertainty: 0.035ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
12-12-2015 10:30 PM
Can you please try with smart explorer and let us know if it resolves your issue.
To get more details on smart explorer please go through the following links
Please let us know if you need more clarification on the above details.
12-12-2015 11:39 PM - edited 12-12-2015 11:45 PM
From the timing report what I can understand is only set-up violation is there. May be packing the logics tightly from the failing path will help to meet timing.
Please go through following link. It gives some recommendations to meet timing closure. Hope this will be helpful to you
If possible please share your archived design file here.
12-13-2015 07:51 AM
That's great. Glad to know your issue is resolved.
As your issue is resolved please close this thread by marking "Accept as solution" to the answer that led you to solution.