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Adventurer
Adventurer
7,726 Views
Registered: ‎04-22-2016

How to get the verilog files in simulation from FIFO Generator?

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Hi.

 

When I generate the FIFO Generator from Core Generator, I found some simulation files.

But these are VHDL not verilog, I also double checked options from Project Options.

 

Project Options-> Generation

Design Entry : Verilog

Vendor : Synplicity

Simulation Files : Behavioral

 

How can I get Verilog files not VHDL files?

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Xilinx Employee
Xilinx Employee
14,712 Views
Registered: ‎07-11-2011

@u24c02

 

Answered here, this may help 

https://forums.xilinx.com/t5/Simulation-and-Verification/can-vivado-generate-verilog-IPCORE-simulation-file/td-p/690328

 

 

-Vanitha

 

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Xilinx Employee
Xilinx Employee
14,713 Views
Registered: ‎07-11-2011

@u24c02

 

Answered here, this may help 

https://forums.xilinx.com/t5/Simulation-and-Verification/can-vivado-generate-verilog-IPCORE-simulation-file/td-p/690328

 

 

-Vanitha

 

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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

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Adventurer
Adventurer
7,718 Views
Registered: ‎04-22-2016
Can you help me how to simulate with fifo stuff files ?
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Xilinx Employee
Xilinx Employee
7,714 Views
Registered: ‎09-20-2012

Hi @u24c02

 

Which simulator are you using?

 

Which version of ISE/Core generator are you using?

 

Based on the simulator you are using you can use one of the scripts located in <proj_dir>\fifo_generator_v9_3\simulation\functional

Thanks,
Deepika.
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Newbie
Newbie
1,574 Views
Registered: ‎02-22-2018

Hi Deepika,

 

I have generated native FIFO and opened IP example design.

All the source files were VHDL files.

Iam using Vivado v2016.3 (64-bit), iam not able to get verilog source files.

 

Also the simulation files in the Example Design are all vhdl files, and not sure how to generate verilog files.

Still there is no support for verilog in v2016.3?

 

Regards

Sunil Kumar

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