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Adventurer
Adventurer
2,639 Views
Registered: ‎04-25-2017

How to make configurable IP core using available vivado IP cores

My problem is,

 

I want to make a IP core with three Ip cores integrated in a vhdl file , out of that for one of the ip core in the vhdl file I want to change a parameter of an internal IP core from outside(from the integrated IP). Is that possible and if possible how to do that?

 

Please help me. 

 

In the following attached files contains the ip core files and hdl files etc.

 

It is related to Jesd ip core and I wanted to a Single Ip core with transport layer and Phy layer integrated one, Out of that the top level integrated vhdl file, I wanted to make an IP in which the QUAD selection which is there in Jesd_PHY IP customisable.

 

Please do the needful by replying soon.

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5 Replies
Moderator
Moderator
2,613 Views
Registered: ‎09-15-2016

Re: How to make configurable IP core using available vivado IP cores

Hi @astrome

 

>>I want to make a IP core with three Ip cores integrated in a vhdl file , out of that for one of the ip core in the vhdl file I want to change a parameter of an internal IP core from outside(from the integrated IP). Is that possible and if possible how to do that?

 

Are the three IP cores integrated in a vhdl file are Xilinx Ips? If yes then you can change the parameter of the IP cores by running the below tcl commands:

set_property CONFIG.<parameter_name> <value> [get_ips <ip_name>]

 

Please refer the below link of UG896, page 28 for more information:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug896-vivado-ip.pdf

 

Hope this helps.

 

Regards

Rohit

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Rohit
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Adventurer
Adventurer
2,569 Views
Registered: ‎04-25-2017

Re: How to make configurable IP core using available vivado IP cores

Hi,

 

You can see in the following attachment of TCL console that parameter which I tried to set is not getting applied. So, how to bring such kind of parameters configurable from outside.

 

Thanks and Regards,

Astrome

 

Screenshot_20170426_102009.png
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Adventurer
Adventurer
2,565 Views
Registered: ‎04-25-2017

Re: How to make configurable IP core using available vivado IP cores

Actually I wanted to make that top level VHDL file as an IP in which one of the parameter in PHY IP core I wanted to configure from that integrated VHDL IP. How do I do that?
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Moderator
Moderator
2,501 Views
Registered: ‎09-15-2016

Re: How to make configurable IP core using available vivado IP cores

Hi @astrome

 

Sorry not all the parameters of the Xilinx IPs can be configured with that command. But you can follow the steps mentioned in UG896 page 115  to edit the IP sources including the parameters:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug896-vivado-ip.pdf

 

Hope this helps.

 

Regards

Rohit

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Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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Adventurer
Adventurer
2,353 Views
Registered: ‎04-25-2017

Re: How to make configurable IP core using available vivado IP cores

I have a doubt that say suppose if I want to use the Xilinx JESD PHY ip by creating several instances with the same component, is it possible to declare an array of instances with JESD PHY ip core?

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