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Observer lvignals
Observer
2,922 Views
Registered: ‎03-27-2013

How to perform simple division of a signal by another signal?

 

For my design I need:

 

- (a) and (b) as two 20 bit input

- (q) as 20 bit output

 

(a) is my dividend and (b) is my divisor and (q) need to be my quotient.

 

For exampe if (a = 17) and (b = 5) then the output should be (q = 3) since q = a/b = 3 when dealing with natural numbers.

 

I tried to do that in a simplified process using intermediate signals s_q for q (see code snippet below), but I kee pgetting this error: Operator <INVALID OPERATOR> must have constant operands or first operand must be power of 2.

 

How can I perform simple division of a signal by another signal (I don't care about the remainder in my case)

 

Example snippet causing the error when synthesizing:

-------------------------------------------------------------

process(clk)
begin
        s_q <= unsigned(a) / unsigned (b);
end process;

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3 Replies
Scholar pratham
Scholar
2,920 Views
Registered: ‎06-05-2013

Re: How to perform simple division of a signal by another signal?

Hi Ivignals,

 

the error you are getting because of divisor should be power of 2,if it's not then xst will throw an error.

 

For  example design  Page NO(183).

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst_v6s6.pdf

 

This might help you.

 

 

Regards,

Prathamsh

 

-Pratham

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Observer lvignals
Observer
2,916 Views
Registered: ‎03-27-2013

Re: How to perform simple division of a signal by another signal?

 

Searching the forum I found out about the divider IP-core so I generated a divider in a test project using the wizard: IP (CORE Generator & Ardchitecture Wizard)

The result is in the picture below but it generated a .xco instead of a VHDL module.

What should I do to get the corresponding VHDL module?

 

Thanks, L.

 

test_divider.jpg

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Xilinx Employee
Xilinx Employee
2,909 Views
Registered: ‎04-16-2012

Re: How to perform simple division of a signal by another signal?

Hi,

 

You have to use .xco file directly in your design.

VHDL behavioral module is not generated with divider core. See datasheet of divider core: http://www.xilinx.com/support/documentation/ip_documentation/div_gen_ds530.pdf 

 

Thanks.

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