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adnan192
Visitor
Visitor
3,941 Views
Registered: ‎05-31-2017

I/O pin standards and clock pin standard for Kintex 7 XC7K325t-2ffg900c (digilent genesys 2)

Hi All,

I am using a Digilent's Genesys 2 (Kintex 7 fpga) Evaluation board. I was not able to give I\O standards for clock pin (AD12 in bank 33) as LVDS or TMDS_33 in I\O planning since these standards aren't available in vivado 2016.2 and 2014.4.

 

Can anyone help me hoe to choose i/o pins standard and clock pin standard? Is there any catalogue for the same

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4 Replies
florentw
Moderator
Moderator
3,936 Views
Registered: ‎11-09-2015

Hi @adnan192,

 

Why aren't you using the xdc file from digilent for you board (see link):

set_property -dict { PACKAGE_PIN AD12 IOSTANDARD LVDS } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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adnan192
Visitor
Visitor
3,920 Views
Registered: ‎05-31-2017

I am using system generator model. So generated project file is opened in vivado and i got synthesize amd implement. Since i don't know how to use XDC files, i was choosing i/o standards from the GUI console. For all other it was LVCMOS33 but for clock pin, i don't know and can't proceed further.
I had copied board ware of genesys2 to installation folder, so i am able to choose the board to which synthsis is aimed.

Anyway i'm trying the XDC way also
thanks
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adnan192
Visitor
Visitor
3,908 Views
Registered: ‎05-31-2017

this is screenshot of error i'm facing after using xdc file as u said and also by choosing froom gui

ERROR.png
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sandrao
Community Manager
Community Manager
3,906 Views
Registered: ‎08-08-2007

The tools are telling you that the IO is single ended so it can't apply a differential IOSTANDARD. Have you instantiated an IBUFDS? I dont see any warning that the tools have removed it.

Thanks,

Sandy


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