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Visitor
Visitor
5,207 Views
Registered: ‎08-29-2013

I cannot get the AXI4-Stream to Video out with Scaler core working...

Hello, everyone. I got a issue with xilinx video core, and tried to solve the problem for several weeks but failed. Could anyone give me some tips for AXI4-Stream to Video core?

 

I tried to implement the Video Scaler core in my project which is a module carried by a data video generater card. In this case, I just used four cores to achieve the simpleset design, which are (1). Video in to Axi4-Stream core, (2) Video Scaler core ,(3). AXI4-Stream to Video Out core, and (4) VTC core implemented as a detectro for (1) and a generator for (3).

 

The problem is that all the outputs of AXI4-Stream to Video Out (ASVO) core (video_data, Vsync, Hsync, video_de) always keep 0 all the time in simulation if I put Video Scaler core in my design. However, I removed Video Scaler core from my project, I got all outputs form ASVO core after locked signal was asserted. I also tried to test Video Scaler core with Video-In to Axi4-Stream core (VIAS) when I removed ASVO core. The video stream also can pass these two cores.

 

As I talked above, I used two VTC cores. One is connected to VIAS core as a detector and the other is connected to ASVO core as a generator. I'm sure I get all ports conntected correctly.

 

The attected is the waveform view from ModelSim, I found the fifo_rst signal is always asserted after one frame. I am not sure how it works. Could anyone help me? Thank you very much.

Regards,
Woody
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Scholar
Scholar
5,186 Views
Registered: ‎02-27-2008

Re: I cannot get the AXI4-Stream to Video out with Scaler core working...

Always in reset means you have a bug in your reset logic.


Find the bug, fix the bug.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Xilinx Employee
Xilinx Employee
5,182 Views
Registered: ‎07-11-2011

Re: I cannot get the AXI4-Stream to Video out with Scaler core working...

Hi,

 

I believe you need to run the simullation for minimum 2 frames for VTC to give the output,   please run for long time or check in hardware ?

 

Regards,

Vanitha.

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Visitor
Visitor
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Registered: ‎08-29-2013

Re: I cannot get the AXI4-Stream to Video out with Scaler core working...


@austin wrote:

Always in reset means you have a bug in your reset logic.


Find the bug, fix the bug.

 

 


Thanks Austin.


Maybe what I said is not clear. The fifo_rst signal is asserted by the Axi4-stream to Video Out core, The problem is that if I test my design with video scaler core, the fifo_rst will be asserted once every three frames. However, if I removed video scaler, the fifo_rst signal is just asserted at the second frame, and the core works correctly.

 

In this case, I don't think there is a bug here. I just think it may be caused by an unknown issue. Is there a problem in my design? In other work, these three cores could be connected together, right? 

 

Thanks.

 

Woody

Regards,
Woody
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Visitor
Visitor
5,170 Views
Registered: ‎08-29-2013

Re: I cannot get the AXI4-Stream to Video out with Scaler core working...


@vsrunga wrote:

Hi,

 

I believe you need to run the simullation for minimum 2 frames for VTC to give the output,   please run for long time or check in hardware ?

 

Regards,

Vanitha.


 

Thanks, Vanitha.

 

I did run the simulation for more than 10 frames, but I got nothing. In the test where I removed the video scaler core, I just get the result after three frames. I am not sure whether the output of Video scaler could be connected to the Axi-S to Video out core as an input. 

 


Regards,

Woody

Regards,
Woody
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Visitor
Visitor
5,060 Views
Registered: ‎10-25-2013

Re: I cannot get the AXI4-Stream to Video out with Scaler core working...

hey ,bro

have you solved this problem ?

may be we are both in the same bug situation.

here is my thread about this problem.

 

http://forums.xilinx.com/t5/General-Technical-Discussion/The-axi4s-vid-out-TRD-project/td-p/373771

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5,034 Views
Registered: ‎11-07-2013

Re: I cannot get the AXI4-Stream to Video out with Scaler core working...

Hello ,dear friend, have you solved your problem now ?   I may got a similar problem  with  you .In my design  ,some of the outputs are normal,such as tvalid,tlast,tuser, but the tdata always keeps 0, I checked  the tready input ,it's always 1.I do not know why.  if you have already solved your probelm, can you share your experience  to me ?  thank   you very much  !   my email  addr  458868525@qq.com

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