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Visitor
Posts: 5
Registered: ‎06-19-2017

IBIS model issues in Hyperlynx

When using the Xilinx Artix IBIS model in Hyperlynx. The IO Models are not selectable.

 

 

 

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Moderator
Posts: 8,497
Registered: ‎02-27-2008

Re: IBIS model issues in Hyperlynx

[ Edited ]

Q: Can I get models for all Xilinx devices?
A: Xilinx provides IBIS models for all Select I/O and Select I/O-Ultra standards. Xilinx can provide (upon SPICE Model License Agreement) HSPICE models for all Select I/O, Select I/O-Ultra, and Rocket I/Os.

 

(from AR #15388)

 

Using the write_ibis command for your design in Vivado, a design specific IBIS file is created which may be imported into Hyperlynx to simulate your design.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor
Posts: 5
Registered: ‎06-19-2017

Re: IBIS model issues in Hyperlynx

I have done this but when the IBIS file is read into Hyperlynx it does not present any "models" to be selected for the IO (as per the image in my post). I exported the IBIS model under "Export IBIS Model" and selected include all models.

 

Here's the command which was run in the Tcl Console.

 

write_ibis C:/Users/c10433/Desktop/IBIS_gen/project_1/DDR3.ibs -truncate 40 -force

 

 

Moderator
Posts: 1,141
Registered: ‎07-23-2015

Re: IBIS model issues in Hyperlynx

@jasonfry 

 

  1. Which version of Hyperlynx?
  2. Do you have the [Model Selector] section in the IBIS file? Can you share the file here?
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Visitor
Posts: 5
Registered: ‎06-19-2017

Re: IBIS model issues in Hyperlynx

We are using Hyperlynx 9.2.

Just checked my IBIS file and there's no [Model Selector] section. THis is probably my issue. How is one generated from Vivado such that it's written into my IBIS file?

 

Thank you

JAson

Moderator
Posts: 1,141
Registered: ‎07-23-2015

Re: IBIS model issues in Hyperlynx

@jasonfry If you have used the MIG IP for the DDR3 and the design is implemented successfully without any DRC's, the write_ibis command should automatically include the [Model Selector] section. I know it does for Kintex/Virtex but need to check for Artix. I believe it should be the same as the underlying IP is the same. 

 

Can you confirm you used the MIG IP for DDR3 and your design successfully implemented before you generated the IBIS Model?

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Visitor
Posts: 5
Registered: ‎06-19-2017

Re: IBIS model issues in Hyperlynx

I've generated the MIG IP and then built my own RTL module and used the IO constraints from the MIG along. I cleaned up all the DRC messages and was able to build (including generating a bitgen). I was able to generate a IBIS file but it did not include the model selector section.

 

Is there another quick means to generate an IBIS model without having to instantiate the MIG and design to get some IBIS models to perform so SI on our CCA. Our goal is to populate the DDR3 memory for future use. I was hoping to avoid doing a full up design to generate these IBIS model.

 

Thanks in advance for your help

Jason

Moderator
Posts: 1,141
Registered: ‎07-23-2015

Re: IBIS model issues in Hyperlynx

@jasonfry The easier route is to use the Generic IBIS models available here: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/device-models/ibis-models/artix-series-fpgas.html

 

If you know the IO Standard and Model to use, just pick the model from the generic file and use it to run your simulations.  

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Visitor
Posts: 5
Registered: ‎06-19-2017

Re: IBIS model issues in Hyperlynx

Thanks for the response. We've had a Xilinx FAE build the MIG for us to ensure everything was good and generate an IBIS model. We ended up with the same result as before (not working). Looking through the IBIS model in the link there's no [model selector].

Moderator
Posts: 8,497
Registered: ‎02-27-2008

Re: IBIS model issues in Hyperlynx

j,

 

Downloading the above file(s) and placing it it the libs subdirectorydirectory foy Hyperlynx brings up all the IO standards through the navigator ...

Austin Lesea
Principal Engineer
Xilinx San Jose