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5,415 Views
Registered: ‎07-07-2016

IO status when power up

Dear Mr./Mrs.

 

Recently, when I use spartan 6 X45 chip to design oscilloscope, which contain another arm chip. When the board is powered up, I need to know that status of the IO pin of the FPGA chip after power up and before configuration finish. The detail situation is: the m0 and m1 pins are set to slave serial configuration status. When the chip is powered up, what status is the IO pins, low, high resistance? When the arm load programme into the FPGA, the config is pulled low, then what status of the IO pin is?

 

If you have any answers for me, please email to me through wlhan.xidian@gmail.com

 

Thanks a lot.

 

Yours 

 

Aaron

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2 Replies
Scholar austin
Scholar
5,391 Views
Registered: ‎02-27-2008

Re: IO status when power up

Aaron,

 

The IO state is tristate after power on, before DONE.  You may select global pullups while powering on with the HSWAP pin.

 

See ug380

Austin Lesea
Principal Engineer
Xilinx San Jose
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5,027 Views
Registered: ‎07-07-2016

Re: IO status when power up

Thanks a lot for your timely and professional answer. Thanks a lot.

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