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Observer lior_glass
Observer
6,636 Views
Registered: ‎01-05-2012

IP Integrator systemverilog interface support

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Hi,

I'd like to extract several AXI4 ports out from the IP Integrator and it is a lot of signals.

So I think to add a user IP to the IP Integrator which will wrap the the AXI4 bus into a signal systemverilog interface.

Does the IP Integrator support systemverilog interface?

Thanks,

Lior Glass

1 Solution

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Teacher muzaffer
Teacher
12,045 Views
Registered: ‎03-31-2012

Re: IP Integrator systemverilog interface support

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This is something I suggested a long time ago. I even gave them my basic implementation of an axi interface for them to use ;-)
They should add a systemverilog option to the languages and generate code which uses interfaces where needed.
Right now, I wrap all Xilinx generated AXI IP with my axi interface wrapper. It's not that bad but I hate to introduce a completely unnecessary hierarchy layer just for some syntactic sugar (albeit tasty).
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3 Replies
Teacher muzaffer
Teacher
12,046 Views
Registered: ‎03-31-2012

Re: IP Integrator systemverilog interface support

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This is something I suggested a long time ago. I even gave them my basic implementation of an axi interface for them to use ;-)
They should add a systemverilog option to the languages and generate code which uses interfaces where needed.
Right now, I wrap all Xilinx generated AXI IP with my axi interface wrapper. It's not that bad but I hate to introduce a completely unnecessary hierarchy layer just for some syntactic sugar (albeit tasty).
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
Scholar markcurry
Scholar
6,435 Views
Registered: ‎09-16-2009

Re: IP Integrator systemverilog interface support

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We do the exact same thing muzaffer.  We've even wrapped the axi_interconnect.  A lot of duplicated work.  Here's hoping Xilinx starts doing this on their own.

 

Regards,

 

Mark

 

Participant egrigor
Participant
297 Views
Registered: ‎12-11-2007

Re: IP Integrator systemverilog interface support

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Yes, this is sorely needed. It's interesting that the IP Integrator GUI takes heavy advantage of interfaces to facilitate the design process, but yet when it comes time for the tool to genrate the Verilog code, it's stuck in the old Verilog standard. Supporting SV output code generation would be a far superior and cleaner approach. Xilinx, please add this capability right away.
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